Method of making semiconductor device having buried bias pad

Patent metadata

Field	Value
Publication number	US-11973083-B2
Application number	US-202217741410-A
Country	US
Kind code	B2
Filing date	May 10, 2022
Priority date	Jul 7, 2020
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

A method of making an integrated circuit includes surrounding a first bias pad with dielectric material of a buried oxide layer. The method includes adding dopants to a layer of semiconductor material over the first bias pad. The method includes depositing a gate dielectric and a gate electrode over a top surface of the layer of semiconductor material. The method includes etching the gate dielectric and the gate electrode to isolate a gate electrode over the layer of semiconductor material. The method includes depositing an inter layer dielectric (ILD) material over the gate electrode and the layer of semiconductor material. The method includes etching at least one bias contact opening down to the first bias pad. The method includes filling the at least one bias contact opening with a bias contact material. The method includes electrically connecting at least one bias contact to an interconnect structure of the semiconductor device.

First claim

What is claimed is:

1. A method of making a semiconductor device, comprising:
surrounding a first bias pad with dielectric material;
adding dopants to a layer of semiconductor material over the first bias pad;
depositing a gate dielectric and a gate electrode material over a top surface of the layer of semiconductor material;
etching the gate dielectric and the gate electrode material to isolate a first gate electrode over the layer of semiconductor material;
depositing an inter layer dielectric (ILD) material over the first gate electrode and the layer of semiconductor material;
etching at least one bias contact opening down to the first bias pad;
filling the at least one bias contact opening with a bias contact material; and
electrically connecting at least one bias contact to an interconnect structure of the semiconductor device.

2. The method of claim 1 , wherein surrounding the first bias pad with dielectric material further comprises:
depositing a first oxide layer over a substrate;
depositing a layer of bias pad material over the first oxide layer;
depositing a second oxide layer over the layer of bias pad material;
isolating the first bias pad from a remainder of the layer of bias pad material by
etching a deep trench isolation structure opening through the second oxide layer and the layer of bias pad material, and
filling the deep trench isolation structure opening with a dielectric material, wherein a deep trench isolation structure extends around a portion of the layer of semiconductor material.

3. The method of claim 1 , wherein adding dopants to the layer of semiconductor material further comprises:
adding dopants to a source well and a drain well of a transistor;
etching substrate contact openings from the first ILD material down to the substrate; and filling the substrate contact openings with a conductive material.

4. The method of claim 1 , wherein etching the gate dielectric and the gate electrode material further comprises isolating a second gate electrode over the layer of semiconductor material, and further comprising surrounding a second bias pad with dielectric material, the second bias pad being below the second gate electrode.

5. The method of claim 4 , wherein the first bias pad has a first bias pad thickness, and the second bias pad has a second bias pad thickness, and the method further comprising modifying the first bias pad thickness to be different from the second bias pad thickness.

6. A method of making a semiconductor device, the method comprising:
manufacturing a bias layer over a buried oxide layer;
growing a layer of semiconductor material over the bias layer;
forming a transistor in the layer of semiconductor material, wherein forming the transistor comprises doping the semiconductor material to define a plurality of doped regions, and the bias layer is between the transistor and a substrate;
forming a first deep trench isolation structure (DTI) extending through the layer of semiconductor material and contacting the substrate; and
forming a first bias contact extending through the layer of semiconductor material and electrically connecting to the bias layer.

7. The method of claim 6 , further comprising forming a dielectric layer over the bias layer, wherein growing the layer of semiconductor material comprises growing the layer of semiconductor material over the dielectric layer.

8. The method of claim 6 , further comprising manufacturing a second bias layer over the buried oxide layer, wherein the second bias layer is spaced from the bias layer in a direction parallel to a top surface of the substrate.

9. The method of claim 8 , further comprising forming a second bias contact extending through the semiconductor layer and electrically connecting to the second bias layer.

10. The method of claim 9 , wherein forming the second bias contact comprises forming the second bias contact on an opposite side of the transistor from the first bias contact.

11. The method of claim 9 , wherein forming the second bias contact comprises forming the second bias contact on a same side of the transistor as the first bias contact.

12. The method of claim 8 , wherein forming the first DTI comprises forming the first DTI between the bias layer and the second bias layer.

13. The method of claim 8 , further comprising forming a second DTI between the bias layer and the second bias layer.

14. The method of claim 13 , wherein forming the second DTI comprises forming the second DTI underneath the transistor.

15. The method of claim 6 , wherein forming the transistor comprises forming a well region in the layer of semiconductor material, wherein the well region partially overlaps the bias layer.

16. A method of making a semiconductor device, the method comprising:
manufacturing a bias layer over a buried oxide layer;
growing a layer of semiconductor material over the bias layer;
forming a transistor in the layer of semiconductor material, wherein forming the transistor comprises doping the semiconductor material to define a plurality of doped regions, and the bias layer is between the transistor and a substrate;
forming a first deep trench isolation structure (DTI) extending through the layer of semiconductor material and contacting the substrate; and
forming a contact extending through the DTI to contact the substrate, wherein the contact is separated from the bias layer.

17. The method of claim 16 , further comprising forming a bias contact extending through the layer of semiconductor material and electrically connecting to the bias layer.

18. The method of claim 17 , wherein forming the bias contact comprises forming the bias contact on an opposite side of the transistor from the contact.

19. The method of claim 17 , wherein forming the bias contact comprises forming the bias contact on a same side of the transistor as the contact.

20. The method of claim 17 , further comprising manufacturing a second bias layer over the buried oxide layer, wherein the second bias layer is between the bias layer and the contact.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Tsmc China Company Ltd

Inventors

• Wu Jian
• Han Feng
• Zhang Shuai

Classifications

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title