Device enhancements for software defined silicon implementations

Patent metadata

Field	Value
Publication number	US-11972269-B2
Application number	US-202218092163-A
Country	US
Kind code	B2
Filing date	Dec 30, 2022
Priority date	Sep 27, 2019
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example non-transitory computer readable medium includes instructions to cause one or more processors to at least generate a first stock keeping unit, associate the first stock keeping unit with a semiconductor device, the first stock keeping unit associated with a first set of features to be provided by the semiconductor device, command the semiconductor device to activate a feature not included in the first set of features to cause the semiconductor device to provide a second set of features, generate a second stock keeping unit for the semiconductor device, and associate the second stock keeping unit with the semiconductor device and the second set of features to be provided by the semiconductor device.

First claim

What is claimed is:

1. At least one non-transitory computer readable medium comprising instructions to cause one or more processors to at least:
associate a first stock keeping unit with a semiconductor device including a plurality of processor cores, respective ones of the processor cores configurable to be active or dormant, the first stock keeping unit associated with a first number of processor cores of the semiconductor device configured to be active, remaining ones of the processor cores to be dormant processor cores;
command the semiconductor device to activate one or more of the dormant processor cores to cause the semiconductor device to provide a second number of processor cores configured to be active; and
generate a second stock keeping unit for the semiconductor device, the second stock keeping unit associated with the semiconductor device having the second number of processor cores configured to be active.

2. The at least one non-transitory computer readable medium of claim 1 , wherein the semiconductor device includes a dormant processing capacity or a dormant feature to be made accessible after activation.

3. The at least one non-transitory computer readable medium of claim 2 , wherein the instructions are to cause the one or processors to manage the dormant feature after activation on the semiconductor device.

4. The at least one non-transitory computer readable medium of claim 1 , wherein the instructions are to cause the one or more processors to command the semiconductor device via a wireless network.

5. The at least one non-transitory computer readable medium of claim 1 , wherein the instructions are to cause the one or more processors to report telemetry data associated with the semiconductor device to a manufacturer management record server.

6. The at least one non-transitory computer readable medium of claim 1 , wherein the second stock keeping unit is an identifier, the identifier associated with a manufacturer management record maintained for the semiconductor device.

7. The at least one non-transitory computer readable medium of claim 2 , wherein the instructions are to cause the one or processors to update the dormant feature in response to feature activation.

8. A method, comprising:
associating a first stock keeping unit with a semiconductor device including a plurality of processor cores, respective ones of the processor cores configurable to be active or dormant, the first stock keeping unit associated with a first number of processor cores of the semiconductor device configured to be dormant, remaining ones of the processor cores to be active processor cores;
commanding the semiconductor device to deactivate one or more of the active processor cores to cause the semiconductor device to provide a second number of processor cores configured to be dormant; and
generating a second stock keeping unit for the semiconductor device, the second stock keeping unit associated with the semiconductor device having the second number of processor cores configured to be dormant.

9. The method of claim 8 , wherein the semiconductor device includes an active processing capacity or an active feature to be made inaccessible after deactivation.

10. The method of claim 9 , further including managing the active feature after deactivation on the semiconductor device.

11. The method of claim 8 , further including commanding the semiconductor device via a wireless network.

12. The method of claim 8 , further including reporting telemetry data associated with the semiconductor device to a manufacturer management record server.

13. The method of claim 8 , wherein the second stock keeping unit is an identifier, the identifier associated with a manufacturer management record maintained for the semiconductor device.

14. The method of claim 9 , further including updating the active feature in response to feature deactivation.

15. A system comprising:
at least one memory;
machine readable instructions; and
processor circuitry to at least one of instantiate or execute the machine readable instructions to:
associate a first stock keeping unit with a processor platform including a plurality of processor cores, respective ones of the processor cores configurable to be active or dormant, the first stock keeping unit associated with a first number of processor cores of the processor platform configured to be active, remaining ones of the processor cores to be dormant processor cores;
command the processor platform to activate one or more of the dormant processor cores to cause the processor platform to provide a second number of processor cores configured to be active; and
generate a second stock keeping unit for the processor platform, the second stock keeping unit associated with the processor platform having the second number of processor cores configured to be active.

16. The system of claim 15 , wherein the processor platform includes a dormant processing capacity or a dormant feature to be made accessible after activation.

17. The system of claim 16 , wherein the processor circuitry is to manage the dormant feature after activation on the processor platform.

18. The system of claim 15 , wherein the processor circuitry is to report telemetry data associated with the processor platform to a manufacturer management record server.

19. The system of claim 15 , wherein the second stock keeping unit is an identifier, the identifier associated with a manufacturer management record maintained for the processor platform.

20. At least one non-transitory computer readable medium comprising instructions to cause one or more processors to at least:
associate a first stock keeping unit with a semiconductor device including a plurality of processor cores, respective ones of the processor cores configurable to be active or dormant, the first stock keeping unit associated with a first number of processor cores of the semiconductor device configured to be dormant, remaining ones of the processor cores to be active processor cores;
command the semiconductor device to deactivate one or more of the active processor cores to cause the semiconductor device to provide a second number of processor cores configured to be dormant; and
generate a second stock keeping unit for the semiconductor device, the second stock keeping unit associated with the semiconductor device having the second number of processor cores configured to be dormant.

21. The at least one non-transitory computer readable medium of claim 20 , wherein the semiconductor device includes an active processing capacity or an active feature to be made inaccessible after deactivation.

22. The at least one non-transitory computer readable medium of claim 21 , wherein the instructions are to cause the one or processors to manage the active feature after deactivation on the semiconductor device.

23. The at least one non-transitory computer readable medium of claim 20 , wherein the instructions are to cause the one or more processors to command the semiconductor device via a wireless network.

24. The at least one non-transitory computer readable medium of claim 20 , wherein the instructions are to cause the one or more processors to report telemetry data associated with the semiconductor device to a manufacturer management record server.

25. The at least one non-transitory computer readable medium of claim 20 , wherein the second stock keeping unit is an identifier, the identifi

Assignees

• Intel Corp

Inventors

• Bartfai-Walcott Katalin Klara
• Berent Arkadiusz
• Chilukuri Vasuki
• Baldwin Mark
• Srinivasan Vasudevan
• Gotowalski Bartosz

Classifications

• G06F9/44505 Primary

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F11/3058 Primary

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F21/105 Primary

  Arrangements for software license management or administration, e.g. for managing licenses at corporate level · CPC title

• H04L9/3247

  involving digital signatures · CPC title

• H04L9/3268

  using certificate validation, registration, distribution or revocation, e.g. certificate revocation list [CRL] · CPC title