Memory controller and method of operating the same

Patent metadata

Field	Value
Publication number	US-11972128-B2
Application number	US-202217872602-A
Country	US
Kind code	B2
Filing date	Jul 25, 2022
Priority date	Dec 12, 2019
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

The present technology relates to a memory controller and a method of operating the same. The memory controller may include a block manager designating a first memory block as an open block, which is driven to program m-bit data per cell, where m is a natural number, an address manager increasing an access count value corresponding to a logical address for the first memory block whenever a program request or a read request including the logical address is received from a host, and a data manager determining a representative attribute of data programmed in the first memory block based on access count values for the logical addresses for the first memory block when a flush request is received from the host. The block manager may determine whether to designate a new open block according to the determined representative attribute.

First claim

What is claimed is:

1. A memory system comprising:
a memory device including first memory blocks and second memory blocks having a larger storage unit per a memory cell than the first memory blocks; and
a memory controller configured to:
designate a first memory block from among the first memory blocks as an open block, determine a representative attribute of the open block when a preset event occurs, and control the memory device to store data, having attributes which are different from each other, stored in the open block in a second memory block from among the second memory blocks when the representative attribute is a cold attribute,
wherein the representative attribute of the open block is a majority attribute of the data stored in the open block among the attributes.

2. The memory system of claim 1 , wherein each of the first memory blocks includes memory cells in which a storage unit is one bit, and
wherein each of the second memory blocks includes memory cells in which a storage unit is two or more bits.

3. The memory system of claim 1 , wherein the memory controller is configured to determine the representative attribute based on a count value indicating a number of times a program operation or a read operation is performed on the open block.

4. The memory system of claim 3 , wherein the memory controller is configured to:
determine the representative attribute as the cold attribute based on the count value being less than a threshold value, and
determine the representative attribute as a hot attribute based on the count value being greater than or equal to the threshold value.

5. The memory system of claim 1 , wherein the preset event comprises an event in which a flush request is received from a host.

6. A memory system comprising:
a memory device including a first memory block, a second memory block having a larger storage unit per a memory cell than the first memory block, and a third memory block having a same storage unit as the first memory block; and
a memory controller configured to:
when data is received from a host, control the memory device to store the data in the first memory block,
when an attribute of the data is cold data after a preset event occurs, control the memory device to store the data stored in the first memory block in the second memory block,
control the memory device to store valid data stored in the first memory block in the third memory block, and
control the memory device to erase the first memory block.

7. The memory system of claim 6 , wherein the first memory block includes memory cells in which a storage unit is one bit, and
wherein the second memory block includes memory cells in which a storage unit is two or more bits.

8. The memory system of claim 6 , wherein the memory controller is configured to, when the attribute is hot data, maintain the data stored in the first memory block.

9. The memory system of claim 6 , wherein the preset event comprises an event in which a flush request is received from the host.

10. The memory system of claim 6 , wherein the memory controller is configured to receive the data with the attribute from the host.

11. The memory system of claim 6 , wherein the memory controller is configured to:
determine that the attribute is hot data when an access frequency of the data is greater than or equal to a reference value, and
determine that the attribute is the cold data when the access frequency is less than the reference value.

12. A memory system comprising:
a memory device including a first memory block, a second memory block having a smaller storage unit per a memory cell than the first memory block, and a third memory block having a same storage unit as the first memory block; and
a memory controller configured to:
control the memory device to store data in the first memory block, and
when an attribute of the data is hot data after a preset event occurs, control the memory device to store the data stored in the first memory block in the second memory block, to store valid data stored in the first memory block in the third memory block, and to erase the first memory block.

13. The memory system of claim 12 , wherein the first memory block includes memory cells in which a storage unit is two or more bits, and
wherein the second memory block includes memory cells in which a storage unit is one bit.

14. The memory system of claim 12 , wherein the memory controller is configured to, when the attribute is cold data, maintain the data stored in the first memory block.

Assignees

• Sk Hynix Inc

Inventors

• Jang In Jong

Classifications

• G06F3/064 Primary

  Management of blocks · CPC title

• G06F3/0617

  in relation to availability · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title