Utilizing a flash memory drive which includes single-level cell flash memory and multi-level cell flash memory

Patent metadata

Field	Value
Publication number	US-10854290-B1
Application number	US-201514751507-A
Country	US
Kind code	B1
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A technique manages data in a flash memory drive which includes single-level cell (SLC) flash memory and multi-level cell (MLC) flash memory. The technique involves performing, within the flash memory drive, data placement operations on data which has been written to the flash memory drive. The technique further involves, based on the data placement operations, storing hot data in the SLC flash memory. The technique further involves, based on the data placement operations, storing cold data in the MLC flash memory, the hot data being accessed more frequently than the cold data. Such hot data and cold data can be distinguished based on access frequency.

First claim

What is claimed is:

1. In a flash memory drive which includes single-level cell (SLC) flash memory and multi-level cell (MLC) flash memory, a method of managing data, the method comprising:
within the flash memory drive, performing data placement operations on data which has been written to the flash memory drive;
based on the data placement operations, storing hot data in the SLC flash memory; and
based on the data placement operations, storing cold data in the MLC flash memory, the hot data being accessed more frequently than the cold data;
wherein performing the data placement operations includes detecting existence of cold data in the SLC flash memory;
wherein storing the cold data in the MLC flash memory includes, in response to detecting existence of the cold data in the SLC flash memory, moving the cold data from the SLC flash memory into the MLC flash memory;
wherein the method further comprises:
detecting occurrence of an idle time event within the flash memory drive; and
wherein moving the cold data from the SLC flash memory into the MLC flash memory is performed in response to detection of the occurrence of the idle time event.

2. A method as in claim 1 wherein performing the data placement operations includes detecting existence of hot data in the SLC flash memory; and
wherein storing the hot data in the SLC flash memory includes, in response to detecting existence of the hot data in the SLC flash memory, maintaining placement of the hot data in the SLC flash memory.

3. A method as in claim 1 wherein detecting the existence of the cold data in the SLC flash memory includes:
identifying the existence of the cold data in the SLC flash memory based on access frequency.

4. A method as in claim 1 wherein detecting the existence of the cold data in the SLC flash memory includes:
identifying the existence of the cold data in the SLC flash memory based on most recent access time.

5. A method as in claim 1 wherein performing the data placement operations further includes detecting existence of hot data in the MLC flash memory; and
wherein storing the hot data in the SLC flash memory includes, in response to detecting the existence of the hot data in the MLC flash memory, moving the hot data from the MLC flash memory into the SLC flash memory.

6. A method as in claim 5 wherein performing the data placement operations further includes detecting existence of cold data in the MLC flash memory; and
wherein storing the cold data in the MLC flash memory includes, in response to detecting the existence of the cold data in the MLC flash memory, maintaining placement of the cold data in the MLC flash memory.

7. A method as in claim 5 wherein moving the hot data from the MLC flash memory into the SLC flash memory is performed in response to detection of the occurrence of the idle time event.

8. A method as in claim 5 wherein detecting the existence of the hot data in the MLC flash memory includes:
identifying the existence of the hot data in the MLC flash memory based on access frequency.

9. A method as in claim 5 wherein detecting the existence of the hot data in the MLC flash memory includes:
identifying the existence of the hot data in the MLC flash memory based on most recent access time.

10. A method as in claim 1 wherein the data written to the flash memory drive is initially saved in the SLC flash memory; and
wherein performing the data placement operations includes labeling data as hot data and cold data while the data is initially saved in the SLC flash memory.

11. A method as in claim 1 wherein the flash memory drive further includes a dynamic random access memory (DRAM) cache;
wherein the data written to the flash memory drive is initially cached in the DRAM cache; and
wherein performing the data placement operations includes labeling data as hot data and cold data while the data is initially cached in the DRAM cache.

12. A flash memory drive, comprising:
single-level cell (SLC) flash memory;
multi-level cell (MLC) flash memory; and
control circuitry coupled to the SLC flash memory and the MLC flash memory, the control circuitry being constructed and arranged to:
perform data placement operations on data which has been written to the flash memory drive,
based on the data placement operations, store hot data in the SLC flash memory, and
based on the data placement operations, store cold data in the MLC flash memory, the hot data being accessed more frequently than the cold data;

wherein the control circuitry, when performing the data placement operations, is constructed and arranged to detect existence of cold data in the SLC flash memory;
wherein the control circuitry, when storing the cold data in the MLC flash memory, is constructed and arranged to, in response to detecting existence of the cold data in the SLC flash memory, move the cold data from the SLC flash memory into the MLC flash memory;
wherein the control circuitry is further constructed and arranged to:
detect occurrence of an idle time event within the flash memory drive; and

wherein moving the cold data from the SLC flash memory into the MLC flash memory is performed in response to detection of the occurrence of the idle time event.

13. A flash memory drive as in claim 12 wherein the control circuitry, when performing the data placement operations, is further constructed and arranged to detect existence of hot data in the MLC flash memory; and
wherein the control circuitry, when storing the hot data in the SLC flash memory, is constructed and arranged to, in response to detecting the existence of the hot data in the MLC flash memory, move the hot data from the MLC flash memory into the SLC flash memory.

14. A flash memory drive as in claim 12 wherein the control circuitry, when performing the data placement operations, is further constructed and arranged to detect existence of hot data in the MLC flash memory; and
wherein the control circuitry, when storing the hot data in the SLC flash memory, is constructed and arranged to, in response to (i) detecting the existence of the hot data in the MLC flash memory and (ii) the idle time event, move the hot data from the MLC flash memory into the SLC flash memory.

15. A flash memory drive as in claim 14 wherein the data written to the flash memory drive is initially saved in the SLC flash memory; and
wherein the control circuitry, when performing the data placement operations, is constructed and arranged to label data as hot data and cold data while the data initially resides in the SLC flash memory.

16. A flash memory drive as in claim 14 , further comprising:
a dynamic random access memory (DRAM) cache coupled to the control circuitry;
wherein the data written to the flash memory drive is initially cached in the DRAM cache; and
wherein the control circuitry, when performing the data placement operations, is constructed and arranged to label data as hot data and cold data while the data is initially cached in the DRAM cache.

17. A data storage enclosure, comprising:
a physical housing;
a communications interface disposed within the physical housing; and
a set of flash memory drives disposed within the physical housing and electronically coupled to the communications interface, each flash memory drive including:
single-level cell (SLC) flash memory,
multi-level cell (MLC) flash memory, and
control circuitry coupled to the SLC flash memory and the MLC flash memory, the control circuitry being constructed and arranged to (i) perform data placement operations on data which has been written to

Assignees

• Emc Ip Holding Co Llc

Inventors

• Wu Bo
• Lei Guangliang
• Von Rhee Scott David

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2212/7204

  Capacity control, e.g. partitioning, end-of-life degradation · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title