Logic unit for a reconfigurable processor

Patent metadata

Field	Value
Publication number	US-11971846-B2
Application number	US-202318109817-A
Country	US
Kind code	B2
Filing date	Feb 14, 2023
Priority date	May 9, 2019
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

A logic unit in an array of processing units is configurable to consume source tokens and a status signal and to produce barrier tokens and an enable signal based on the source tokens and the status signal.

First claim

The invention claimed is:

1. A processing system, comprising:
a logic unit in an array of processing units, the logic unit configurable to consume source tokens and a status signal and to produce barrier tokens and an enable signal based on the source tokens and the status signal.

2. The processing system of claim 1 , further configured to comprise a control bus configurable by configuration data to form signal routes in a control barrier network coupled to processing units in the array of processing units.

3. The processing system of claim 2 , wherein the control bus comprises a configurable interconnect configurable by the configuration data to connect lines on the control bus carrying barrier tokens produced on the outputs of logic units as source tokens to inputs of logic units that consume source tokens.

4. The processing system of claim 2 , wherein the processing units in the array of processing units are configurable by the configuration data to execute execution fragments.

5. The processing system of claim 2 , wherein the control bus is configurable to form signal routes connecting the output of one logic unit in the plurality of logic units as a source token to inputs of more than one logic unit in the plurality of logic units.

6. The processing system of claim 2 , wherein the control bus is configurable to form signal routes providing source tokens sourced from more than one logic unit in the plurality of logic units to inputs of one logic unit in the plurality of logic units.

7. The processing system of claim 2 , the logic unit comprising:
a token store having inputs and outputs;
a configurable input circuit configurable to connect selected lines in the control bus and a status signal line of the processing unit to inputs of the token store; and
a token output circuit configurable to provide a barrier token to the control bus in response to a first configurable combination of the outputs of the token store.

8. The processing system of claim 2 , the logic unit comprising:
a token store having inputs and outputs;
a configurable input circuit configurable to connect selected lines in the control bus and a status signal line of the processing unit to inputs of the token store;
a token output circuit configurable to provide a barrier token to the control bus in response to a first configurable combination of the outputs of the token store;
a feedback circuit configurable to provide a feedback signal in response to a second configurable combination of the outputs of the token store, to clear the token store; and
an enable circuit to provide the enable signal to the processing unit in response to outputs of the token store.

9. The processing system of claim 2 , comprising a data bus interconnecting the processing units in the array of processing units, and separate from the control bus.

10. The processing system of claim 9 , wherein the data bus comprises a packet switched network.

Assignees

• Sambanova Systems Inc

Inventors

• Prabhakar Raghu
• Shah Manish K
• Sivaramakrishnan Ram
• Nataraja Pramod
• Jackson David Brian
• Grohoski Gregory Frederick

Classifications

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title

• G06F9/522

  Barrier synchronisation · CPC title

• G06F15/17325

  Synchronisation; Hardware support therefor (intertask synchronisation G06F9/52) · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F15/8007 Primary

  single instruction multiple data [SIMD] multiprocessors · CPC title