Exposing PCIE configuration spaces as ECAM compatible

Patent metadata

Field	Value
Publication number	US-11971839-B2
Application number	US-202217869272-A
Country	US
Kind code	B2
Filing date	Jul 20, 2022
Priority date	Jul 20, 2022
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

Disclosed are various approaches for exposing peripheral component interconnect express (PCIe) configuration space implementations as Enhanced Configuration Access Mechanism (ECAM)-compatible. In some examples, a bridge device is identified on a segment corresponding to a root complex of a computing device. An endpoint device is connected to a bus downstream from the bridge device. A synthetic segment identifier is assigned to the bus once the endpoint device is identified as connected to the bus. Synthetic address data is generated for the endpoint device. The synthetic address data includes the synthetic segment identifier for the bus and sets a bus identifier of the bus to zero regardless of a hierarchical position of the bus in a standard peripheral component interconnect express (PCIe) bus hierarchy.

First claim

Therefore, the following is claimed:

1. A non-transitory computer-readable medium comprising machine-readable instructions, wherein the instructions, when executed by at least one processor, cause a computing device to at least:
identify, by firmware instructions executed by the at least one processor, that a bridge device is on a segment corresponding to a root complex of the computing device;
detect, by the firmware instructions, that an endpoint device is connected to a bus downstream from the bridge device;
assign, by the firmware instructions, a synthetic segment identifier to the bus based at least in part on the endpoint device being identified as connected to the bus; and
generate, by the firmware instructions, synthetic address data that includes the synthetic segment identifier, and sets a bus identifier of the bus to zero regardless of a hierarchical position of the bus in a standard peripheral component interconnect express (PCIe) bus hierarchy.

2. The non-transitory computer-readable medium of claim 1 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
load, by the firmware instructions, ACPI data into a memory of the computing device, the ACPI data comprising at least a portion of the synthetic address data.

3. The non-transitory computer-readable medium of claim 2 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
access, by an operating system, the endpoint device based at least in part on the ACPI data comprising the at least the portion of the synthetic address data.

4. The non-transitory computer-readable medium of claim 2 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
mark, by the firmware instructions, the bridge device as disabled in the ACPI data.

5. The non-transitory computer-readable medium of claim 1 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
identify, by the firmware instructions, a filtering problem or a minimum granule size problem that causes a function of the endpoint device to errantly respond to a nonzero device identifier.

6. The non-transitory computer-readable medium of claim 5 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
add, by the firmware instructions, 0x8000 to a base address corresponding to the synthetic segment identifier.

7. The non-transitory computer-readable medium of claim 6 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
generate, by the firmware instructions, an input output remapping table that indicates a predetermined instruction that handles functions corresponding to a synthetic segment base address modification comprising the 0x8000 added to the base address.

8. A system, comprising:
a computing device comprising at least one processor; and
at least one memory comprising machine-readable instructions, wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
identify, by firmware instructions executed by the at least one processor, that a bridge device is on a segment corresponding to a root complex of the computing device;
detect, by the firmware instructions, that an endpoint device is connected to a bus downstream from the bridge device;
assign, by the firmware instructions, a synthetic segment identifier to the bus based at least in part on the endpoint device being identified as connected to the bus; and
generate, by the firmware instructions, synthetic address data that includes the synthetic segment identifier, and sets a bus identifier of the bus to zero.

9. The system of claim 8 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
load, by the firmware instructions, ACPI data into a memory of the computing device, the ACPI data comprising at least a portion of the synthetic address data.

10. The system of claim 9 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
access, by an operating system, the endpoint device based at least in part on the ACPI data comprising the at least the portion of the synthetic address data.

11. The system of claim 9 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
mark, by the firmware instructions, the bridge device as disabled in the ACPI data.

12. The system of claim 8 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
identify, by the firmware instructions, a filtering problem or a minimum granule size problem that causes a function of the endpoint device to errantly respond to a nonzero device identifier.

13. The system of claim 12 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
add, by the firmware instructions, 0x8000 to a base address corresponding to the synthetic segment identifier.

14. The system of claim 13 , wherein the instructions, when executed by the at least one processor, cause the computing device to at least:
generate, by the firmware instructions, an input output remapping table that indicates a predetermined instruction to handle functions corresponding to a synthetic segment base address modification comprising the 0x8000 added to the base address.

15. A method comprising:
identifying, by firmware instructions executed by at least one processor, that a bridge device is on a segment corresponding to a root complex of a computing device;
detecting, by the firmware instructions, that an endpoint device is connected to a bus downstream from the bridge device;
assigning, by the firmware instructions, a synthetic segment identifier to the bus based at least in part on the endpoint device being identified as connected to the bus; and
generating, by the firmware instructions, synthetic address data that includes the synthetic segment identifier, and sets a bus identifier of the bus to zero.

16. The method of claim 15 , further comprising:
loading, by the firmware instructions, ACPI data into a memory of the computing device, the ACPI data comprising at least a portion of the synthetic address data.

17. The method of claim 16 , further comprising:
accessing, by an operating system, the endpoint device based at least in part on the ACPI data comprising the at least the portion of the synthetic address data.

18. The method of claim 16 , further comprising:
marking, by the firmware instructions, the bridge device as disabled in the ACPI data.

19. The method of claim 15 , further comprising:
identifying, by the firmware instructions, a filtering problem or a minimum granule size problem that causes a function of the endpoint device to errantly respond to a nonzero device identifier.

20. The method of claim 19 , further comprising:
adding, by the firmware instructions, 0x8000 to a base address corresponding to the synthetic segment identifier.

Assignees

• VMware LLC
• Vmware Inc

Inventors

• Warkentin Andrei

Classifications

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/404

  with address mapping · CPC title