Magnetic tunnel junction device

Patent metadata

Field	Value
Publication number	US-11968908-B2
Application number	US-202217854289-A
Country	US
Kind code	B2
Filing date	Jun 30, 2022
Priority date	Jan 17, 2020
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

First claim

What is claimed is:

1. A device comprising:
a first inter-metal dielectric over a semiconductor substrate, the semiconductor substrate comprising active devices;
a first conductive feature extending through the first inter-metal dielectric, the first conductive feature electrically connected to the active devices;
a first bottom electrode over the first conductive feature;
a first magnetic tunnel junction stack over the first bottom electrode;
a first top electrode comprising:
a first conductive layer over the first magnetic tunnel junction stack;
a dielectric layer over the first conductive layer; and
a second conductive layer over the dielectric layer;

a second inter-metal dielectric over the first top electrode; and
a second conductive feature extending through the second inter-metal dielectric, the second conductive feature contacting the first top electrode.

2. The device of claim 1 further comprising:
a third conductive feature extending through the first inter-metal dielectric;
a second bottom electrode over the third conductive feature;
a second magnetic tunnel junction stack over the second bottom electrode;
a second top electrode comprising:
a third conductive layer over the second magnetic tunnel junction stack; and
a fourth conductive layer over the third conductive layer; and

a fourth conductive feature extending through the second inter-metal dielectric, the fourth conductive feature contacting the second top electrode,
wherein the second inter-metal dielectric is over the second top electrode, and
wherein a combined thickness of the third conductive layer and the fourth conductive layer is equal to a combined thickness of the first conductive layer, the dielectric layer, and the second conductive layer.

3. The device of claim 2 further comprising:
a spacer disposed on sidewalls of the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the dielectric layer, the first magnetic tunnel junction stack, the second magnetic tunnel junction stack, the first bottom electrode, and the second bottom electrode.

4. The device of claim 2 further comprising an interfacial oxide layer at an interface of the third conductive layer and the fourth conductive layer, the interfacial oxide layer being flat.

5. The device of claim 2 further comprising an interfacial oxide layer at an interface of the third conductive layer and the fourth conductive layer, the interfacial oxide layer being uneven.

6. The device of claim 1 further comprising:
a third inter-metal dielectric over the semiconductor substrate, the third inter-metal dielectric adjacent the first inter-metal dielectric;
a third conductive feature extending through the third inter-metal dielectric, the third conductive feature electrically connected to the active devices; and
a fourth conductive feature extending through the second inter-metal dielectric, the fourth conductive feature contacting the third conductive feature.

7. A device comprising:
a first memory cell comprising:
a first bottom electrode;
a first magnetic tunnel junction stack on the first bottom electrode; and
a first top electrode on the first magnetic tunnel junction stack, the first top electrode comprising first conductive layers and a first dielectric layer between the first conductive layers, the first dielectric layer having a first thickness;

a second memory cell comprising:
a second bottom electrode;
a second magnetic tunnel junction stack on the second bottom electrode; and
a second top electrode on the second magnetic tunnel junction stack, the second top electrode comprising second conductive layers and a second dielectric layer between the second conductive layers, the second dielectric layer having a second thickness, the second thickness less than the first thickness.

8. The device of claim 7 further comprising:
an inter-layer dielectric adjacent the first memory cell and the second memory cell; and
a conductive feature extending through the inter-layer dielectric, a top surface of the conductive feature planar with a top surface of the first top electrode and a top surface of the second top electrode.

9. The device of claim 7 further comprising:
an inter-layer dielectric above the first memory cell and the second memory cell;
a first conductive feature extending through the inter-layer dielectric, the first conductive feature contacting the first top electrode; and
a second conductive feature extending through the inter-layer dielectric, the second conductive feature contacting the second top electrode.

10. The device of claim 7 , wherein the first dielectric layer has a flat interface with an underlying first conductive layer, and the second dielectric layer has a flat interface with an underlying second conductive layer.

11. The device of claim 7 , wherein the first dielectric layer has a flat interface with an underlying first conductive layer, and the second dielectric layer has an uneven interface with an underlying second conductive layer.

12. The device of claim 7 further comprising:
an inter-metal dielectric above a semiconductor substrate;
a first conductive feature extending through the inter-metal dielectric, the first bottom electrode disposed on the first conductive feature; and
a second conductive feature extending through the inter-metal dielectric, the second bottom electrode disposed on the second conductive feature.

13. The device of claim 12 further comprising:
a first spacer on a first top surface of the inter-metal dielectric and on a first sidewall of the first memory cell; and
a second spacer on a second top surface of the inter-metal dielectric and on a second sidewall of the second memory cell, the second top surface disposed further from the semiconductor substrate than the first top surface.

14. The device of claim 12 , wherein the inter-metal dielectric comprises a same material as the first dielectric layer.

15. The device of claim 13 , wherein a thickness of the first top electrode is equal to a thickness of the second top electrode.

16. The device of claim 13 further comprising:
a third memory cell between the first memory cell and the second memory cell, the third memory cell comprising:
a third bottom electrode;
a third magnetic tunnel junction stack on the third bottom electrode; and
a third top electrode on the third magnetic tunnel junction stack, the third top electrode comprising third conductive layers and a third dielectric layer between the third conductive layers, the third dielectric layer having the first thickness.

17. A device comprising:
an inter-layer dielectric over a semiconductor substrate, the semiconductor substrate comprising active devices;
a first inter-metal dielectric over the inter-layer dielectric;
a first conductive feature extending through the first inter-metal dielectric, the first conductive feature electrically connected to the active devices;
a first bottom electrode over the first conductive feature;
a first magnetic tunnel junction stack over the first bottom electrode;
a first top electrode comprising:
a first conductive layer over the first magnetic tunnel junction stack; and
a second conductive layer over the first conductive layer;

a spacer disposed on sidewalls of the first conductive layer, the second conductive layer, the first magnetic tunnel junction stack, and the first bottom electrode;
a second inter-metal dielectric having a first portion and a second portion, the first portion disposed over the inter-l

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Tai-Yen
• Wei Hui-Hsien
• Lin Han-Ting
• Yang Sin-Yi
• Chen Yu-Shu
• Chang An-Shen
• Fu Qiang
• Wang Chen-Jung

Classifications

• G11C11/1657

  Word-line or row circuits · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H10B61/20

  comprising components having three or more electrodes, e.g. transistors · CPC title

• H10B61/10

  comprising components having two electrodes, e.g. diodes or MIM elements · CPC title