Display substrate, manufacturing method thereof, and display apparatus

Patent metadata

Field	Value
Publication number	US-11968879-B2
Application number	US-202017260562-A
Country	US
Kind code	B2
Filing date	Mar 27, 2020
Priority date	Mar 27, 2020
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

A display substrate, a manufacturing method thereof and a display apparatus are disclosed. The display substrate includes a silicon base substrate and a color film layer disposed on the silicon base substrate. A plurality of metal traces for connecting a display area and a cathode ring with a bonding area respectively are contained in the silicon base substrate. The color film layer includes a first align mark, and the first align mark has a hollowed-out structure. A projection of the first align mark on the silicon base substrate and projections of the metal traces on the silicon base substrate include overlapping areas.

First claim

What we claim is:

1. A display substrate, comprising: a silicon base substrate and a color film layer disposed on the silicon base substrate, the silicon base substrate containing a plurality of metal traces for connecting a display area and a cathode ring with a bonding area respectively; the color film layer comprising a first align mark, and the first align mark having a hollowed-out structure,
wherein a projection of the first align mark on the silicon base substrate and projections of the metal traces on the silicon base substrate comprise overlapping areas,
wherein the display area comprise a light-emitting structural layer disposed on the silicon base substrate, and the light-emitting structural layer comprises a reflective layer, an anode layer, an organic light-emitting layer and a cathode layer which are sequentially stacked,
wherein a driving circuit layer is disposed in the silicon base substrate in the display area and comprises a first scanning line, a first power line, a data line, a switching transistor and a driving transistor; a control electrode of the switching transistor is connected with the first scanning line, a first electrode of the switching transistor is connected with the data line, a second electrode of the switching transistor is connected with a control electrode of the driving transistor, and a first electrode of the driving transistor is connected with the first power line; the switching transistor is configured to receive a data signal transmitted by the data line under the control of a first scanning signal output by the first scanning line, to make the control electrode of the driving transistor receive the data signals, and the driving transistor is configured to generate a corresponding current at the second electrode under the control of the data signal received by the control electrode thereof, and
wherein the metal traces and the driving circuit layer are disposed on the same layer.

2. The display substrate according to claim 1 , wherein the color film layer in the display area comprises a first color unit, a second color unit and a third color unit arranged in an array; the color film layer outside the display area comprises at least one of the first color unit, the second color unit and the third color unit forming a complete surface.

3. The display substrate according to claim 2 , wherein the color film layer outside the display area comprises a first color unit layer and a second color unit layer which are sequentially stacked, and the first color unit layer and the second color unit layer comprise mutually penetrating apertures to form the first align mark through the apertures.

4. The display substrate according to claim 3 , wherein the first color unit layer is a blue color filter unit layer and the second color unit layer is a red color filter unit layer.

5. The display substrate according to claim 1 , wherein the cathode ring comprises a power supply electrode layer disposed on the silicon base substrate, a reflective layer disposed on a side of the power supply electrode layer away from the silicon base substrate, an anode layer disposed on a side of the reflective layer away from the power supply electrode layer, and a cathode layer disposed on a side of the anode layer away from the reflective layer.

6. The display substrate according to claim 1 , wherein the bonding area comprises a bonding electrode layer disposed on the silicon base substrate and an insulating layer for covering the bonding electrode layer, and a via exposing a bonding electrode in the bonding electrode layer is disposed in the insulating layer.

7. The display substrate according to claim 6 , wherein the bonding area further comprises a second align mark layer disposed on the silicon base substrate, and the second align mark layer and the bonding electrode layer are disposed on the same layer.

8. A display apparatus comprising the display substrate of claim 1 .

9. A method for manufacturing a display substrate, comprising:
providing a display substrate motherboard, wherein the display substrate motherboard comprises at least one display substrate area, the display substrate area comprises a silicon base substrate, and a plurality of metal traces for connecting a display area and a cathode ring with a bonding area respectively are contained in the silicon base substrate;
forming a color film layer on the silicon base substrate, wherein the color film layer comprises a first align mark, the first align mark has a hollowed-out structure, and a projection of the first align mark on the silicon base substrate and projections of the metal traces on the silicon base substrate comprise overlapping areas; and
cutting the display substrate motherboard to obtain a separate display substrate,
wherein the display area comprise a light-emitting structural layer disposed on the silicon base substrate, and the light-emitting structural layer comprises a reflective layer, an anode layer, an organic light-emitting layer and a cathode layer which are sequentially stacked,
wherein a driving circuit layer is disposed in the silicon base substrate in the display area and comprises a first scanning line, a first power line, a data line, a switching transistor and a driving transistor; a control electrode of the switching transistor is connected with the first scanning line, a first electrode of the switching transistor is connected with the data line, a second electrode of the switching transistor is connected with a control electrode of the driving transistor, and a first electrode of the driving transistor is connected with the first power line; the switching transistor is configured to receive a data signal transmitted by the data line under the control of a first scanning signal output by the first scanning line, to make the control electrode of the driving transistor receive the data signals, and the driving transistor is configured to generate a corresponding current at the second electrode under the control of the data signal received by the control electrode thereof, and
wherein the metal traces and the driving circuit layer are disposed on the same layer.

10. The manufacturing method according to claim 9 , wherein the color film layer in the display area comprises a first color unit, a second color unit and a third color unit arranged in an array; the color film layer outside the display area comprises at least one of the first color unit, the second color unit and the third color unit forming a complete surface.

11. A display substrate, comprising: a silicon base substrate and a color film layer disposed on the silicon base substrate, the silicon base substrate containing a plurality of metal traces for connecting a display area and a cathode ring with a bonding area respectively; the color film layer comprising a first align mark, and the first align mark having a hollowed-out structure,
wherein a projection of the first align mark on the silicon base substrate and projections of the metal traces on the silicon base substrate comprise overlapping areas,
wherein a length of the first align mark is 50 to 150 microns, a width of the first align mark is 20 to 50 microns; a width of the metal trace is 50 to 150 nanometers, and a spacing between adjacent metal traces is 30 to 50 nanometers, and
wherein a ratio of an area of the metal traces exposed by the first align mark to an area of the first align mark is greater than or equal to 80%.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Li Yunlong
• Lu Pengcheng
• Ao Yu
• Zhu Zhijian
• Tian Yuanlan
• Zhang Dacheng

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/607

  Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10K59/1315

  comprising structures specially adapted for lowering the resistance · CPC title

• H10K59/878

  comprising reflective means · CPC title