Spread spectrum chopping for sigma delta modulators

Patent metadata

Field	Value
Publication number	US-11967972-B2
Application number	US-202217735740-A
Country	US
Kind code	B2
Filing date	May 3, 2022
Priority date	May 3, 2022
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

Chopping techniques that suppress fold-back into the signal band and spreads the offset across the spectrum are described. By using various techniques, chopping may be performed with a variable frequency clock to spread the offset across the signal spectrum. Spreading the offset across the signal spectrum means that there are no longer large spurious tones at a few frequencies.

First claim

The claimed invention is:

1. An analog-to-digital converter (ADC) circuit to generate a digital output signal, the ADC circuit comprising:
an oversampled ADC circuit having an input coupled to receive an analog input signal and generate a first digital output signal, the oversampled ADC including:
a chop switch that receives and is controlled by a variable frequency chop signal; and
a chop signal generating circuit to generate the variable frequency chop signal;
a sample rate converter circuit to receive the first digital output signal at a first sample rate and generate a second digital output signal at a second sample rate; and
a digital filter circuit including a decimator to process and decimate the second digital output signal and generate a filtered digital output signal.

2. The ADC circuit of claim 1 , wherein the oversampled ADC circuit includes a sigma-delta (SD) ADC circuit, the SD ADC circuit including:
an integrator circuit including an amplifier circuit, wherein the chop switch is coupled to an input of the amplifier circuit.

3. The ADC circuit of claim 2 , wherein the chop signal generating circuit includes a cascade of differentiators.

4. The ADC circuit of claim 2 , wherein the chop signal generating circuit includes a second or higher order digital sigma-delta modulator.

5. The ADC circuit of claim 4 , wherein the second or higher order digital sigma-delta modulator circuit includes a one-bit second or higher order digital sigma-delta modulator.

6. The ADC circuit of claim 4 , wherein the second or higher order digital sigma-delta modulator circuit includes a multi-bit second or higher order digital sigma-delta modulator.

7. The ADC circuit of claim 6 , comprising:
a pulse width modulator generator to receive an output of the multi-bit second or higher order digital sigma-delta modulator and generate the variable frequency chop signal.

8. The ADC circuit of claim 7 , wherein the multi-bit second or higher order digital sigma-delta modulator is a feedback system that forms a loop, and wherein the pulse width modulator generator is positioned within the loop.

9. The ADC circuit of claim 2 , wherein the chop signal generating circuit includes a counter circuit to:
randomly select a number;
divide a sampling frequency by the number to generate a clock signal; and
generate the variable frequency chop signal using the clock signal.

10. A method of operating an analog-to-digital converter (ADC) circuit to generate a digital output signal, the method comprising:
receiving an analog input signal at a summing node of a sigma-delta (SD) ADC circuit, wherein the SD ADC circuit includes an integrator circuit having an amplifier circuit and a chop switch coupled to an input of the amplifier circuit;
receiving, using the integrator circuit, an output of the summing node;
generating a variable frequency chop signal and operating the chop switch at the variable frequency chop signal;
receiving, via sample rate converter circuit, a first digital output signal of the SD ADC circuit at a first sample rate and generating a second digital output signal at a second sample rate; and
processing and decimating, via a digital filter circuit including a decimator, the second digital output signal and generating a filtered digital output signal.

11. The method of claim 10 , wherein generating the variable frequency chop signal and operating the chop switch at the variable frequency chop signal includes:
generating the variable frequency chop signal using a cascade of differentiators.

12. The method of claim 11 , wherein generating the variable frequency chop signal using the cascade of differentiators the cascade of differentiators includes:
generating the variable frequency chop signal using a third-order cascade of differentiators.

13. The method of claim 10 , wherein generating the variable frequency chop signal and operating the chop switch at the variable frequency chop signal includes:
generating the variable frequency chop signal and operating the chop switch at the variable frequency chop signal using a second or higher order digital sigma-delta modulator.

14. The method of claim 13 , wherein generating the variable frequency chop signal and operating the chop switch at the variable frequency chop signal using the second or higher order digital sigma-delta modulator includes:
generating the variable frequency chop signal and operating the chop switch at the variable frequency chop signal using a one-bit second or higher order digital sigma-delta modulator.

15. The method of claim 13 , wherein generating the variable frequency chop signal and operating the chop switch at the variable frequency chop signal using the second or higher order digital sigma-delta modulator includes:
generating the variable frequency chop signal and operating the chop switch at the variable frequency chop signal using a multi-bit second or higher order digital sigma-delta modulator.

16. The method of claim 15 , comprising:
receiving, using a pulse width modulator generator, an output of the multi-bit second or higher order digital sigma-delta modulator and generating the variable frequency chop signal.

17. The method of claim 10 , wherein generating a variable frequency chop signal and operating the chop switch at the variable frequency chop signal includes:
randomly selecting a number;
dividing a sampling frequency by the number to generate a clock signal; and
generating the variable frequency chop signal using the clock signal.

18. An analog-to-digital converter (ADC) circuit to generate a digital output signal, the ADC circuit comprising:
a sigma-delta (SD) ADC circuit having an input coupled to receive an analog input signal and generate a first digital output signal, the SD ADC including:
an integrator circuit including an amplifier circuit and a chop switch, the chop switch coupled to an input of the amplifier circuit, wherein the chop switch receives and is controlled by a variable frequency chop signal; and
means for generating the variable frequency chop signal;
a sample rate converter circuit to receive the first digital output signal at a first sample rate and generate a second digital output signal at a second sample rate; and
a digital filter circuit including a decimator to process and decimate a representation of the digital output signal and generate a filtered digital output signal.

19. The ADC circuit of claim 18 , comprising:
a sample rate converter circuit to receive the digital output signal at a first sample rate and generate the representation of the digital output signal at a second sample rate.

20. The ADC circuit of claim 18 , wherein the means for generating the variable frequency chop signal includes a second or higher order digital sigma-delta modulator.

Assignees

• Analog Devices International Unlimited Co

Inventors

• Maurino Roberto Sergio Matteo
• Vyas Bhargav R
• Shaik Ayesha

Classifications

• H03M3/498 Primary

  Variable sample rate · CPC title

• H03M3/34 Primary

  by chopping · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/356

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M3/494) · CPC title

• H03M3/328

  using dither · CPC title