Analog computer architecture for fast function optimization

Patent metadata

Field	Value
Publication number	US-11967951-B2
Application number	US-202117171824-A
Country	US
Kind code	B2
Filing date	Feb 9, 2021
Priority date	Nov 30, 2018
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

An analog circuit for solving optimization algorithms comprises three voltage controlled current sources and three capacitors, operatively coupled in parallel to the three voltage controlled current sources, respectively. The circuit further comprises a first inductor, operatively coupled in series between a first pair of the capacitors and the voltage controller current sources and a second pair of the capacitors and the voltage controller current sources. The circuit further comprises a second inductor, operatively coupled in series between the second pair of the capacitors and the voltage controller current sources and a third pair of the capacitors and the voltage controller current sources.

First claim

What is claimed is:

1. An analog circuit for solving optimization algorithms, the analog circuit comprising:
a plurality of voltage controlled current sources;
a plurality of capacitors, wherein each of the plurality of capacitors is coupled in parallel with at least one voltage controlled current source of the plurality of voltage controlled current sources;
a first inductor, operatively coupled between a first pair of the plurality of capacitors and the plurality of voltage controlled current sources and a second pair of the plurality of capacitors and the plurality of voltage controlled current sources; and
a second inductor, operatively coupled between the second pair of the plurality of capacitors and the plurality of voltage controlled current sources and a third pair of the plurality of capacitors and the plurality of voltage controlled current sources, wherein the analog circuit is part of a model-predictive control scheme.

2. The analog circuit of claim 1 , wherein the analog circuit is to solve the optimization algorithms in less than 500 milliseconds.

3. The analog circuit of claim 2 , wherein the analog circuit is to solve the optimization algorithms in less than 500 nanoseconds.

4. The analog circuit of claim 1 , wherein the analog circuit is to solve distributed optimization algorithms.

5. The analog circuit of claim 1 , wherein the analog circuit is to solve the optimization algorithms with multi-variable cost functions.

6. The analog circuit of claim 5 , wherein the multi-variable cost functions are non-convex.

7. The analog circuit of claim 1 , wherein the analog circuit is implemented by a field programmable analog array (FPAA).

8. The analog circuit of claim 7 , wherein the FPAA is configured digitally.

9. A field programmable analog array (FPAA) for solving optimization algorithms, configured to comprise:
a plurality of voltage controlled current sources;
a plurality of capacitors, each capacitor operatively coupled in parallel to one of the plurality of voltage controlled current sources, respectively, to form a plurality of voltage controlled current source and capacitor pairs; and
a plurality of energy-storage components, each energy-storage component of the plurality of energy-storage components operatively coupled between the plurality of voltage controller current source and capacitor pairs, wherein the FPAA is part of a model-predictive control scheme.

10. The FPAA of claim 9 , wherein the FPAA is configured digitally.

11. The FPAA of claim 9 , wherein the plurality of energy-storage components is a plurality of inductors.

12. The FPAA of claim 10 , wherein the plurality of energy-storage components is a plurality of operational amplifiers.

13. The FPAA of claim 9 , wherein the FPAA is to solve the optimization algorithms in less than 500 milliseconds.

14. The FPAA of claim 13 , wherein the FPAA is to solve the optimization algorithms in less than 500 nanoseconds.

15. The FPAA of claim 9 , wherein the FPAA is to solve the distributed optimization algorithms.

16. The FPAA of claim 9 , wherein the FPAA is to solve the optimization algorithms with multi-variable cost functions.

17. The FPAA of claim 16 , wherein the FPAA is to increase a probability of solving for a local minimum when the multi-variable cost functions are non-convex.

18. A method comprising:
receiving an optimization problem to be solved; and
generating, by a processing device, a digital program for a field programmable analog array (FPAA), wherein an output of the digital program is to configure the FPAA to execute the optimization problem in an analog manner as part of a model-predictive control scheme.

19. The method of claim 18 , wherein to configure the FPAA to execute the optimization problem the output of the digital program is to configure a plurality of switches of the FPAA.

Assignees

• Xerox Corp

Inventors

• Matei Ion
• Feldman Aleksandar
• De Kleer Johan

Classifications

• H03K19/17748 Primary

  Structural details of configuration resources · CPC title

• G06G7/122

  for optimisation, e.g. least square fitting, linear programming, critical path analysis, gradient method · CPC title

• G06G7/32

  for solving of equations {or inequations; for matrices} · CPC title