Extrinsic field termination structures for improving reliability of high-voltage, high-power active devices

Patent metadata

Field	Value
Publication number	US-11961888-B2
Application number	US-201917263366-A
Country	US
Kind code	B2
Filing date	Aug 6, 2019
Priority date	Aug 6, 2018
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

Extrinsic structures formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. An example integrated device including such an intrinsic structure includes a semiconductor device having an active region in a conduction layer, an isolation region in the conduction layer, an insulating layer formed over at least a portion of the active region and over at least a portion of the isolation region, a via outside the active region, and a conductive interconnect. The isolation region extends around the semiconductor device in an area outside the active region. The via extends through the insulating layer and down to the isolation region in the conduction layer, and the conductive interconnect is formed directly on the isolation region in the conduction layer.

First claim

What is claimed is:

1. An integrated device comprising:
a semiconductor device having an active region in a conduction layer;
an isolation region in the conduction layer, the isolation region extending around the semiconductor device in an area outside the active region;
an insulating layer formed over at least a portion of the active region and over at least a portion of the isolation region;
a via outside the active region, the via extending through the insulating layer and down to the isolation region in the conduction layer; and
a conductive interconnect within the via outside the active region and directly on the isolation region in the conduction layer.

2. The integrated device of claim 1 , wherein the conductive interconnect comprises titanium directly on the isolation region in the conduction layer.

3. The integrated device of claim 1 , further comprising a plurality of additional semiconductor devices, wherein the conductive interconnect connects an electrode of the semiconductor device to additional electrodes of the plurality of additional semiconductor devices of a same type as the electrode.

4. The integrated device of claim 1 , wherein the semiconductor device is a transistor or a diode.

5. The integrated device of claim 1 , wherein the semiconductor device comprises gallium-nitride material.

6. The integrated device of claim 1 , wherein the semiconductor device can output between 50 Watts and 1000 Watts.

7. The integrated device of claim 1 , wherein an electrode of the semiconductor device is circular or quasi-circular.

8. The integrated device of claim 1 , wherein the isolation region comprises damaged semiconductor material.

9. The integrated device of claim 1 , wherein:
the semiconductor device comprises a transistor;
the semiconductor device comprises gallium-nitride material; and
the transistor has a gate leakage current of less than 1 microamp per millimeter of peripheral length after 10 hours of operating at 5 Watts per millimeter of peripheral length, 50 Volts drain-to-source bias, and 235° C. operating environment temperature.

10. A method comprising:
forming a semiconductor device having an active region in a conduction layer over a substrate;
forming an insulating layer over at least a portion of the active region and over at least a portion of the conduction layer outside the active region;
creating an isolation region in the conduction layer, the isolation region extending around the semiconductor device in an area outside the active region;
forming a via through the insulating layer outside the active region, the via extending down to the isolation region in the conduction layer; and
depositing a conductive interconnect directly on the isolation region within the via outside the active region.

11. The method of claim 10 , wherein the conductive interconnect comprises titanium directly on the isolation region in the conduction layer.

12. The method of claim 10 , wherein forming the semiconductor device comprises forming a transistor or a diode.

13. The method of claim 10 , wherein forming the semiconductor device comprises depositing gallium-nitride material.

14. The method of claim 10 , wherein creating the isolation region comprises performing ion implantation to damage crystalline semiconductor.

15. The method of claim 10 , further comprising:
forming a plurality of additional semiconductor devices of a same kind as the semiconductor device over the substrate; and
connecting the semiconductor device and the plurality of additional semiconductor devices to operate in parallel.

16. The method of claim 15 , further comprising depositing the conductive interconnect to connect together electrodes of a same type for the semiconductor device and the plurality of additional semiconductor devices.

17. An integrated device comprising:
an active region in a conduction layer;
an isolation region extending around the active region;
an insulating layer formed over at least a portion of the active region and over at least a portion of the isolation region;
a via outside the active region, the via extending through the insulating layer and down to the isolation region; and
a conductive interconnect within the via outside the active region and directly on the isolation region.

18. The integrated device of claim 17 , wherein the conductive interconnect comprises titanium directly on the isolation region.

19. The integrated device of claim 17 , wherein an electrode of the integrated device is circular or quasi-circular.

20. The integrated device of claim 17 , wherein the isolation region comprises damaged semiconductor material.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Hanson Allen W
• Lian Chuanxin
• Struble Wayne Mack

Classifications

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title