Semiconductor device

Patent metadata

Field	Value
Publication number	US-11961885-B2
Application number	US-202217943337-A
Country	US
Kind code	B2
Filing date	Sep 13, 2022
Priority date	Jul 26, 2018
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2≥(L1/2) is satisfied.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a base;
a first field effect transistor, wherein the first field effect transistor is disposed on a first side of the base, and wherein the first field effect transistor includes:
a first channel portion;
a second channel portion, wherein the first channel portion is disposed between the second channel portion and the base; and

a first insulation layer, wherein the first insulation layer is disposed between the first channel portion and the base;
a second field effect transistor, wherein the second field effect transistor is disposed on the first side of the base, and wherein the second field effect transistor includes:
a channel forming layer;
a gate insulation layer, wherein at least a portion of the gate insulation layer is between the channel forming layer and the base;
a gate electrode, wherein at least a portion of the gate electrode is between the gate insulation layer and the base; and
a second insulation layer,

wherein the second insulation layer is between the gate electrode and the base, and
wherein a thickness of the second insulation layer is larger than a thickness of the first insulation layer.

2. The semiconductor device of claim 1 , further comprising:
at least first and second instances of the first field effect transistor.

3. The semiconductor device of claim 2 , further comprising:
at least first and second instances of the second field effect transistor.

4. The semiconductor device of claim 3 , wherein, in the second instance of the first field effect transistor, a portion of the first insulation layer is disposed between the first channel portion and the second channel portion.

5. The semiconductor device of claim 4 , wherein the first and second instances of the first field effect transistor each further include a third channel portion, wherein the second channel portion is disposed between the third channel portion and the first channel portion.

6. The semiconductor device of claim 5 , wherein each of the channel portions of the instances of the first field effect transistor have a nanowire structure.

7. The semiconductor device of claim 6 , wherein each of the channel portions of the instances of the first field effect transistor are at least partially surrounded by a corresponding gate insulation film.

8. The semiconductor device of claim 7 , wherein each of the channel forming layers of the first and second instances of the second field effect transistor are surrounded by a corresponding gate insulation layer.

9. The semiconductor device of claim 6 , wherein the channel portions and associated gate insulation films of the first instance of the first field effect transistor are surrounded by a gate electrode, and wherein the channel portions and associated gate insulation films of the second instance of the first field effect transistor are at least partially surrounded by a gate electrode.

10. The semiconductor device of claim 6 , wherein each of the channel portions of the first and second instances of the first field effect transistor is separated from a nearest other channel portion by a distance L 1 , wherein a thickness of the channel forming layer of the first instance of the second field effect transistor is equal to Ta, and wherein T 2 ≥(L 1 /2).

11. The semiconductor device of claim 3 , wherein each of the channel forming layers of the first and second instances of the second field effect transistor are surrounded by a corresponding gate insulation layer.

12. The semiconductor device of claim 1 , wherein each of the channel portions of the first field effect transistor are at least partially surrounded by a corresponding gate insulation film.

13. The semiconductor device of claim 12 , wherein the channel portions and associated gate insulation films of the first field effect transistor are at least partially surrounded by a gate electrode.

14. The semiconductor device of claim 1 , wherein each of the channel portions of the first field effect transistor have a nanowire structure.

15. The semiconductor device of claim 14 , wherein each of the channel portions of the first field effect transistor is separated from a nearest other channel portion by a distance L 1 , wherein a thickness of the channel forming layer of the second field effect transistor is equal to Ta, and wherein T 2 ≥(L 1 /2).

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Gocho Tetsuo
• Fukuzaki Yuzo
• Miyake Shinichi
• Tomida Kazuyuki

Classifications

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title

• H10D30/6743

  Silicon · CPC title