Semiconductor device

Patent metadata

Field	Value
Publication number	US-2021280673-A1
Application number	US-201917261226-A
Country	US
Kind code	A1
Filing date	Jun 18, 2019
Priority date	Jul 26, 2018
Publication date	Sep 9, 2021
Grant date	—

Abstract

A semiconductor device includes a base, a first FET 10n that includes at least two channel structure portions 11n laminated, the channel structure portions 11n each including a channel portion 13n having a nanowire structure 12n, a gate insulation film, and a gate electrode 27n, and a second FET 20n that includes a channel forming layer 23n, a gate insulation layer, and a gate electrode 27n. The first FET 10n and the second FET 20n are provided above the base. The channel portions 13n of the first FET 10n are disposed apart from each other in a laminating direction of the channel structure portions 11n. Assuming that each of a distance between the channel portions 13n of the first FET 10n is a distance L1 and that a thickness of the gate insulation layer of the second FET 20n is a thickness T2, T2≥(L1/2) is satisfied.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a base; a first field effect transistor that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion that has a nanowire structure or a nanosheet structure, a gate insulation film that surrounds the channel portion, and a gate electrode that surrounds at least a part of the gate insulation film; and a second field effect transistor that includes a channel forming layer, a gate insulation layer surrounding the channel forming layer, and a gate electrode surrounding at least a part of the gate insulation layer, wherein the first field effect transistor and the second field effect transistor are provided above the base, the channel portions of the first field effect transistor are disposed apart from each other in a laminating direction of the channel structure portions, and assuming that each of a distance between the channel portions of the first field effect transistor is a distance L 1 and that a thickness of the gate insulation layer of the second field effect transistor is a thickness T 2 ,
T 2 ≥( L 1 /2)

is satisfied.

2 . The semiconductor device according to claim 1 , wherein T 2 ≥1.1×(L 1 /2) is satisfied.

3 . The semiconductor device according to claim 1 , wherein, assuming that a distance between a surface of the base and the channel forming layer of the second field effect transistor is a distance L 2 ,
L 2 >L 1 , and L 2 ≥T 2

are satisfied.

4 . The semiconductor device according to claim 3 , wherein L 2 ≥2×L 1 is satisfied.

5 . The semiconductor device according to claim 1 , wherein, assuming that a thickness of each of the gate insulation films of the first field effect transistor is a thickness T 1 ,
T 2 ≥2× T 1

is satisfied.

6 . The semiconductor device according to claim 1 , wherein, assuming that a thickness of each of the channel portions is T 1-CH and that a thickness of the channel forming layer is T 2-CH ,
T 2-CH ≥2 ×T 1-CH

is satisfied.

7 . The semiconductor device according to claim 1 , wherein
at least a part of a channel portion in a lowermost layer constituting the first field effect transistor is surrounded by a first gate electrode, and a channel portion other than the channel portion in the lowermost layer is surrounded by a second gate electrode.

8 . The semiconductor device according to claim 1 , wherein
the second field effect transistor includes an n-channel type field effect transistor and a p-channel type field effect transistor, a channel forming layer of the n-channel type field effect transistor includes silicon, and a channel forming layer of the p-channel type field effect transistor includes silicon or silicon-germanium.

9 . The semiconductor device according to claim 1 , wherein
the first field effect transistor includes an n-channel type field effect transistor and a p-channel type field effect transistor, a channel portion of the n-channel type field effect transistor includes silicon, and a channel portion of the p-channel type field effect transistor includes silicon-germanium, germanium, or InGaAs.

10 . A semiconductor device comprising:
a base; a first field effect transistor that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion that has a nanowire structure or a nanosheet structure, a gate insulation film that surrounds the channel portion, and a gate electrode that surrounds at least a part of the gate insulation film; and a second field effect transistor that includes a channel forming layer, a gate insulation layer formed on a top surface and a side surface of the channel forming layer, and a gate electrode formed on at least a top surface of the gate insulation layer, wherein the first field effect transistor and the second field effect transistor are provided above the base, the channel portions of the first field effect transistor are disposed apart from each other in a laminating direction of the channel structure portions, and an insulation material layer is formed between a surface of the base and a bottom surface of the channel forming layer constituting the second field effect transistor.

11 . The semiconductor device according to claim 10 , wherein reverse bias is applied to the base at a portion facing the bottom surface of the channel forming layer via the insulation material layer.

12 . The semiconductor device according to claim 10 , wherein, assuming that a thickness of each of the channel portions is T 1-CH and that a thickness of the insulation material layer is T Ins ,
0.2 ≤T 1-CH /T Ins ≤2

is satisfied.

13 . The semiconductor device according to claim 10 , wherein at least one semiconductor layer is formed between the channel forming layer and the insulation material layer in the second field effect transistor.

14 . The semiconductor device according to claim 13 , wherein an interlayer insulation layer is formed between the channel forming layer and the semiconductor layer and between the semiconductor layers.

15 . The semiconductor device according to claim 13 , wherein the semiconductor layer has a conductivity type opposite to a conductivity type of the channel forming layer.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Gocho Tetsuo
• Fukuzaki Yuzo
• Miyake Shinichi
• Tomida Kazuyuki

Classifications

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title

• H10D30/6743

  Silicon · CPC title