Finfet based capacitors and resistors and related apparatuses, systems, and methods
US-2020235249-A1 · Jul 23, 2020 · US
US11961836B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11961836-B2 |
| Application number | US-201816147205-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 28, 2018 |
| Priority date | Sep 28, 2018 |
| Publication date | Apr 16, 2024 |
| Grant date | Apr 16, 2024 |
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An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.
Opening claim text (preview).
What is claimed is: 1. An integrated circuit structure, comprising: a plurality of fins extending above a surface of a substrate along a first direction, the plurality of fins spaced apart from one another; a gate over the plurality of fins, the gate along a second direction substantially orthogonal with the first direction; an insulating layer that surrounds and is in contact with respective ones of the plurality of fins in-between the substrate and the gate; an N-type well located in the substrate below the plurality of fins; and an N-type doping in the substrate between the plurality of fins and the N-type well, the N-type doping extending vertically from the substrate to only a portion a height of the respective ones of the plurality of fins that extend above the surface of the substrate and below the gate, wherein the N-type doping has a doping concentration of 2e18-7e18. 2. The integrated circuit structure of claim 1 , wherein the second N type doping has a doping depth of 70-120 nm. 3. The integrated circuit structure of claim 1 , wherein the plurality of fins comprise a first set of fins having a first fin height and a second set of fins having a second fin height, where the second fin height is less than the first fin height. 4. The integrated circuit structure of claim 3 , wherein the first fin height and the second fin height are measured between the substrate and respective gates. 5. The integrated circuit structure of claim 4 , wherein the first fin height is 120-140 nm and the second fin height is 45-50 nm. 6. A FinFET varactor, comprising: an N-type well within a substrate; a plurality of fins along a first direction extending above a surface of the substrate over the N-type well, the plurality of fins spaced apart from one another; a plurality of gates over the plurality of fins that extend above the surface of a substrate, the plurality of gates along a second direction substantially orthogonal with the first direction; an insulating layer that surrounds and is in contact with respective ones of the plurality of fins in-between the substrate and the plurality of gates; and an N-type doping in the substrate between the plurality of fins and the N-type well, the N-type doping extending vertically from the substrate to only a portion a height of the respective ones of the plurality of fins that extend above the surface of the substrate and below the plurality of gates, wherein the N-type doping has a doping concentration of 2e18-7e18. 7. The FinFET varactor of claim 6 , wherein the N-type doping has a doping depth of 70-120 nm. 8. The FinFET varactor of claim 6 , wherein the plurality of fins comprise a first set of fins having a first fin height and a second set of fins having a second fin height, where the second fin height is less than the first fin height. 9. The FinFET varactor of claim 8 , wherein the first fin height and the second fin height are measured between the substrate and respective gates. 10. The FinFET varactor of claim 9 , wherein the first fin height is 120-140 nm and the second fin height is 45-50 nm.
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