Method of forming a molded substrate electronic package and structure

Patent metadata

Field	Value
Publication number	US-11961794-B2
Application number	US-202017130182-A
Country	US
Kind code	B2
Filing date	Dec 22, 2020
Priority date	Mar 20, 2015
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.

First claim

What is claimed is:

1. A method of forming an electronic component, comprising:
providing lands that are laterally separated by spaces, the lands comprising a conductor, land top surfaces, and land bottom surfaces opposite to the land top surfaces;
forming an insulator within the spaces, the insulator having an insulator top surface and an insulator bottom surface, the insulator top surface covering each of the land top surfaces, wherein:
the land bottom surfaces are exposed through the insulator bottom surface;

removing the insulator from the insulator top surface to expose the land top surfaces to provide a substrate having a substrate top surface adjacent to the land top surfaces and a substrate bottom surface adjacent to the land bottom surfaces;
depositing conductive patterns over the substrate top surface and coupled to the land top surfaces;
coupling an electronic device to the conductive patterns; and
forming a package body encapsulating the substrate top surface, at least portions of the electronic device, and at least portions of the conductive patterns,
wherein:
providing the lands comprises:
providing a work piece having a work piece top side and a work piece bottom side;
selectively removing portions of the work piece extending inward from the work piece top side to define the spaces; and
after forming the insulator and before removing the insulator from the insulator top surface:
first, globally removing a first portion of the work piece from the work piece bottom side; and
second, selectively removing a second portion of the work piece from the work piece bottom side to expose the insulator bottom surface and to define the land bottom surfaces.

2. The method of claim 1 , wherein:
removing the insulator comprises providing the substrate top surface substantially co-planar with the land top surfaces.

3. The method of claim 1 , further comprising:
providing an offset between the land bottom surfaces and the insulator bottom surface so that the insulator bottom surface is recessed inward with respect to the land bottom surfaces; and
forming conductive bumps over the land bottom surfaces,
wherein:
the lands comprise side surfaces exposed from the insulator proximate to the insulator bottom surface; and
the conductive bumps contact the side surfaces and the insulator bottom surface.

4. The method of claim 1 , further comprising:
providing an offset between each of the land bottom surfaces and the insulator bottom surface so that the land bottom surfaces are recessed inward with respect to the insulator bottom surface.

5. The method of claim 1 , further comprising:
providing an offset between the land bottom surfaces and the insulator bottom surface so that the insulator bottom surface is recessed inward with respect to the land bottom surfaces.

6. The method of claim 1 , further comprising:
forming conductive bumps over the land bottom surfaces.

7. The method of claim 1 , wherein:
forming the insulator comprises forming a molded resin insulator.

8. The method of claim 1 , wherein:
forming the conductive patterns comprises:
forming a masking layer on at least portions of the insulator top surface; and
electroplating the conductive patterns using the land top surfaces as seed regions.

9. The method of claim 1 , wherein:
coupling the electronic device comprises attaching a semiconductor component to the conductive patterns in a flip-chip configuration.

10. The method of claim 1 , wherein:
coupling the electronic device comprises coupling the electronic device comprising a first major surface, a second major surface opposite to the first major surface, and a side surface connecting the first major surface to the second major surface;
the side surface of the electronic device defines a perimeter; and
all the lands are inside the perimeter and are external interconnect structures for the electronic component.

11. A method for forming an electronic component, comprising:
providing lands that are laterally separated by spaces, the lands having land top surfaces, opposing land bottom surfaces, and comprising a conductor;
forming an insulator within the spaces, the insulator having an insulator top surface and an insulator bottom surface, the insulator top surface covering the land top surfaces, wherein:
the land bottom surfaces are exposed through the insulator bottom surface;

reducing thickness of the insulator from the insulator top surface inward to provide a reduced thickness insulator top surface, wherein:
the land top surfaces are exposed in the reduced thickness insulator top surface;

forming conductive patterns over the reduced thickness insulator top surface and coupled to the land top surfaces;
coupling an electronic device to the conductive patterns; and
forming a package body encapsulating at least portions of the electronic device;
wherein:
coupling the electronic device comprises coupling a semiconductor component to the conductive patterns in a flip-chip configuration;
the semiconductor component comprises a first major surface, a second major surface opposite to the first major surface, and a side surface connecting the first major surface to the second major surface;
the side surface of the semiconductor component define a perimeter; and
all the lands of the electronic component are inside the perimeter and external interconnects for the electronic component.

12. The method of claim 11 , wherein:
providing the lands comprises:
providing a substrate having a substrate top surface and an opposing substrate bottom surface; and
selectively removing portions of the substrate extending inward from the substrate top surface to define the spaces; and

the method further comprises removing part of the substrate from the substrate bottom surface before reducing the thickness of the insulator.

13. The method of claim 11 , further comprising:
providing an offset between the land bottom surfaces and the insulator bottom surface so that the land bottom surfaces are recessed inward with respect to the insulator bottom surface.

14. The method of claim 11 , further comprising:
providing an offset between the land bottom surfaces and the insulator bottom surface so that the insulator bottom surface is recessed inward with respect to the land bottom surfaces.

15. The method of claim 14 , further comprising:
providing conductive bumps over the land bottom surfaces,
wherein:
the lands comprise side surfaces exposed from the insulator proximate to the insulator bottom surface; and
the conductive bumps contact the side surfaces and the insulator bottom surface.

16. A method for forming an electronic component, comprising:
providing a carrier substrate comprising a first surface, an opposing second surface, and a conductive film over the opposing second surface;
providing lands adjacent to the conductive film, the lands laterally separated by spaces, the lands having land top surfaces adjacent to the conductive film and opposing land bottom surfaces;
providing an insulator within the spaces and having an insulator top surface and an insulator bottom surface, wherein the land bottom surfaces are exposed through the insulator bottom surface;
removing the carrier substrate while leaving the conductive film in place adjacent to the land top surfaces;
patterning the conductive film to provide conductive patterns coupled to the land top surfaces;
coupling an electronic device to the conductive patterns; and
forming a package body encapsulating at least portions of the electronic device.

Assignees

• Amkor Tech Singapore Holding Pte Ltd
• Amikor Tech Singapore Holding Pte Ltd

Inventors

• Bang Won Bae
• Kim Byong Jin
• Kim Gi Jeong
• Chung Ji Young

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/117 Primary

  the substrate having spherical bumps for external connection · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title