Semiconductor devices and related methods

Patent metadata

Field	Value
Publication number	US-11961775-B2
Application number	US-202217982713-A
Country	US
Kind code	B2
Filing date	Nov 8, 2022
Priority date	Jun 3, 2019
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a first module, comprising:
a first substrate comprising a first cavity and a first internal terminal;
a first device stack in the first cavity and comprising a plurality of electronic devices, wherein a first electronic device of the plurality of electronic devices comprises a first device terminal;
a first encapsulant in the first cavity and covering lateral sides of the plurality of electronic devices of the first device stack; and
a first internal interconnect in the first encapsulant and coupled with the first internal terminal and the first device terminal;
wherein:
the first substrate comprises a substrate shelf;
the first substrate comprises a substrate ledge portion and a substrate vertical portion extending from the substrate ledge portion, the substrate ledge portion including a ledge;
the substrate ledge portion defines a first width of the first cavity and the substrate vertical portion defines a second width of the first cavity greater than the first width of the first cavity; and
the substrate shelf comprises the ledge and the ledge includes the first internal terminal.

2. The semiconductor device of claim 1 , wherein:
the first encapsulant covers a top side of the ledge and a lateral side of the ledge.

3. The semiconductor device of claim 1 , wherein:
a top side of the substrate shelf is uncovered by the first encapsulant.

4. The semiconductor device of claim 1 , wherein:
the first encapsulant is exposed through a bottom side of the first substrate.

5. The semiconductor device of claim 1 , wherein:
the first electronic device is exposed through a bottom side of the first substrate.

6. The semiconductor device of claim 1 , comprising:
a second module over the first module, wherein the second module comprises:
a second substrate comprising a second cavity and a second internal terminal;
a second device stack in the second cavity and comprising a second plurality of electronic devices, wherein a second electronic device of the second plurality of electronic devices comprises a second device terminal;
a second encapsulant in the second cavity and covering lateral sides of the second plurality of electronic devices of the second device stack; and
a second internal interconnect in the second encapsulant and coupled with the second internal terminal and the second device terminal;
wherein the second substrate comprises a second substrate shelf.

7. The semiconductor device of claim 6 , wherein:
a lateral side of the first substrate is flush with a lateral side of the second substrate.

8. The semiconductor device of claim 6 , wherein:
a lateral side of the first substrate is offset from a lateral side of the second substrate.

9. The semiconductor device of claim 6 , comprising:
a base substrate, wherein the first module and the second module are over the base substrate; and
a main encapsulant over the base substrate and covering lateral sides of the first module and the second module.

10. The semiconductor device of claim 9 , comprising:
a first conductive adhesive between a top side of the base substrate and a bottom side of the first substrate; and
a second conductive adhesive between a top side of the first substrate and a bottom side of the second substrate.

11. A semiconductor device, comprising:
a first module, comprising:
a first substrate comprising a top side, a bottom side, a first cavity in the first substrate, and a first conductive structure;
a first device stack comprising a first electronic device in the first cavity and a second electronic device external to the first cavity, wherein the first electronic device comprises a first device terminal and the second electronic device comprises a second device terminal;
a first encapsulant in the first cavity;
a second encapsulant over the top side of the first substrate, wherein the first encapsulant covers a lateral side of the first electronic device and the second encapsulant covers a lateral side of the second electronic device;
a first internal interconnect in the first encapsulant and coupled with the first device terminal and the first conductive structure; and
a second internal interconnect in the second encapsulant and coupled with the second device terminal and the first conductive structure;
wherein a lateral side of the first encapsulant and a lateral side of the second encapsulant are flush with a lateral side of the first substrate.

12. The semiconductor device of claim 11 , wherein the first module further comprises:
a first external interconnect at the bottom side of the first substrate; and
a second external interconnect at the top side of the first substrate and in an opening of the second encapsulant.

13. The semiconductor device of claim 12 , wherein:
the first encapsulant covers the bottom side of the first substrate and covers a lateral side of the first external interconnect.

14. The semiconductor device of claim 12 , wherein:
a top side of the second external interconnect is below a top side of the second encapsulant.

15. The semiconductor device of claim 12 , comprising:
a second module over the first module and comprising:
a second substrate comprising a top side, a bottom side, a second cavity in the second substrate, and a second conductive structure;
a second device stack comprising a third electronic device in the second cavity and a fourth electronic device external to the second cavity, wherein the third electronic device comprises a third device terminal and the fourth electronic device comprises a fourth device terminal;
a third encapsulant in the second cavity;
a fourth encapsulant over the top side of the second substrate, wherein the third encapsulant covers a lateral side of the third electronic device and the fourth encapsulant covers a lateral side of the fourth electronic device;
a third internal interconnect in the third encapsulant and coupled with the third device terminal and the second conductive structure;
a fourth internal interconnect in the fourth encapsulant and coupled with the fourth device terminal and the second conductive structure; and
a third external interconnect at the bottom side of the second substrate;

wherein the third external interconnect is coupled with the second external interconnect in the opening of the second encapsulant.

16. A semiconductor device, comprising:
a base substrate comprising a top side, a bottom side, and a plurality of internal base terminals;
a first module, comprising:
a first substrate comprising a first cavity and a first conductive structure;
a first device stack comprising a first electronic device located in the first cavity, the first electronic device including a first device terminal;
a first encapsulant in the first cavity and covering a lateral side of the first electronic device; and
a first internal interconnect in the first encapsulant and coupled with the first conductive structure and the first device terminal;

a second module over the first module and comprising:
a second substrate comprising a second cavity and a second conductive structure;
a second device stack comprising a second electronic device located in the second cavity, the second electronic device including a second device terminal;
a second encapsulant in the second cavity and covering a lateral side of the second electronic device; and
a second internal interconnect in the second encapsulant and coupled with the second conductive structure and the second device terminal;

a main encapsulant over t

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Han Gyu Wan
• Bang Won Bae
• Lee Ju Hyung
• Chang Min Hwa
• Park Dong Joo
• Khim Jin Young
• Kim Jae Yun
• Hong Se Hwan
• Yu Seung Jae
• Bowers Shaun
• Lim Gi Tae
• Cho Byoung Woo
• Choi Myung Jea
• Lee Seul Bee
• Kang Sang Goo
• Park Kyung Rok

Classifications

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/07507

  the auxiliary member being a temporary substrate, e.g. a removable substrate · CPC title