Semiconductor device and method of making a wafer-level chip-scale package

Patent metadata

Field	Value
Publication number	US-11961764-B2
Application number	US-202117231591-A
Country	US
Kind code	B2
Filing date	Apr 15, 2021
Priority date	Oct 2, 2012
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant over the semiconductor die;
removing the encapsulant over a side surface of the semiconductor die; and
forming a fan-in interconnect structure over the semiconductor die by,
forming a first insulating layer over the semiconductor die,
forming a second insulating layer over the first insulating layer,
forming a conductive layer over the first insulating layer and second insulating layer, and
forming a third insulating layer over the conductive layer;

wherein a side surface of the first insulating layer, a side surface of the second insulating layer, a side surface of the third insulating layer, a side surface of the semiconductor die, and a side surface of the encapsulant are all coplanar to each other.

2. The method of claim 1 , further including forming the fan-in interconnect structure over the semiconductor die prior to depositing the encapsulant.

3. The method of claim 1 , wherein a footprint of the fan-in interconnect structure is totally contained within a footprint of the semiconductor die.

4. The method of claim 1 , wherein forming the fan-in interconnect structure includes:
forming the conductive layer to fan in from contact pads of the semiconductor die; and
forming the third insulating layer over the conductive layer prior to singulating the semiconductor die, wherein a discrete portion of the second insulating layer is limited to within a footprint of the semiconductor die.

5. The method of claim 1 , further including depositing the encapsulant over a back surface of the semiconductor die.

6. The method of claim 5 , further including removing the encapsulant from over the back surface of the semiconductor die.

7. The method of claim 6 , further including disposing a backside insulating layer over the back surface of the semiconductor die after removing the encapsulant from over the back surface of the semiconductor die.

8. A semiconductor device, comprising:
a semiconductor die including a contact pad;
an encapsulant deposited over the semiconductor die; and
a fan-in interconnect structure formed over the semiconductor die, wherein the fan-in interconnect structure includes,
a first insulating layer formed over the semiconductor die including a first opening formed through the first insulating layer to expose the contact pad,
a second insulating layer formed over the first insulating layer including a second opening formed through the second insulating layer to expose the contact pad,
a conductive layer formed over the first insulating layer and second insulating layer, wherein the conductive layer extends through the first opening and second opening to contact the contact pad, and
a third insulating layer formed over and directly on the conductive layer and second insulating layer, wherein side surfaces of the semiconductor die, first insulating layer, second insulating layer, and third insulating layer are all coplanar to each other.

9. The semiconductor device of claim 8 , wherein the encapsulant extends over a side surface of the fan-in interconnect structure.

10. The semiconductor device of claim 8 , further including:
an under-bump metallization (UBM) formed over the conductive layer; and
a conductive bump disposed on the UBM.

11. The semiconductor device of claim 8 , wherein a footprint of the fan-in interconnect structure is totally contained within a footprint of the semiconductor die.

12. The semiconductor device of claim 8 , wherein:
the conductive layer is formed to fan in from contact pads of the semiconductor die; and
the third insulating layer is formed over the conductive layer with a discrete portion of the third insulating layer limited to within a footprint of the semiconductor die.

13. A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited over the semiconductor die, wherein a side surface of the semiconductor die is exposed from the encapsulant; and
a fan-in interconnect structure formed over the semiconductor die, wherein the fan-in interconnect structure includes,
a first insulating layer formed over the semiconductor die,
a second insulating layer formed over the first insulating layer,
a conductive layer formed over the first insulating layer and second insulating layer, and
a third insulating layer formed over the conductive layer;

wherein a side surface of the first insulating layer, a side surface of the second insulating layer, a side surface of the third insulating layer, a side surface of the semiconductor die, and a side surface of the encapsulant are all coplanar to each other.

14. The semiconductor device of claim 13 , further including:
an under-bump metallization (UBM) formed over the conductive layer; and
a conductive bump disposed on the UBM.

15. The semiconductor device of claim 13 , wherein a footprint of the fan-in interconnect structure is completely contained within a footprint of the semiconductor die.

16. The semiconductor device of claim 13 , wherein:
the conductive layer fans in from contact pads of the semiconductor die; and
a discrete portion of the third insulating layer is limited to within a footprint of the semiconductor die.

17. The semiconductor device of claim 13 , wherein the encapsulant remains only over a back surface of the semiconductor die.

Assignees

• Stats Chippac Pte Ltd

Inventors

• Strothmann Thomas J
• Pricolo Damien M
• Shim Il Kwon
• Lin Yaojian
• Wirtz Heinz-Peter
• Yoon Seung Wook
• Marimuthu Pandi C

Classifications

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title