Liquid crystal display panel comprising pixel circuit reducing power consumption

Patent metadata

Field	Value
Publication number	US-11961492-B2
Application number	US-202017264331-A
Country	US
Kind code	B2
Filing date	Jul 22, 2020
Priority date	Dec 13, 2019
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A pixel circuit, a display panel, a display device and a driving method. The pixel circuit includes: a first control module, a latch module, a second control module, a first input module and a second input module. The first control module provides a signal on a data line to a first node under control of a signal of first gate line. The latch module latches signals of the first node and a second node. The second control module provides signal on the data line to a third node under control of a signal on a second gate line. The first input module provides a signal of a reference signal terminal to a pixel electrode under control of signal of the first node. The second input module provides a signal of the third node to the pixel electrode under control of signal of the second node.

First claim

What is claimed is:

1. A pixel circuit, comprising: a first control circuit, a latch circuit, a second control circuit, a first input circuit and a second input circuit; wherein
the first control circuit is configured to provide a signal on a data line to a first node under a control of a signal on a first gate line;
the latch circuit is configured to latch signals of the first node and a second node;
the second control circuit is configured to provide the signal on the data line to a third node under a control of a signal on a second gate line;
the first input circuit is configured to provide a signal of a reference signal terminal to a pixel electrode under a control of the signal of the first node; and
the second input circuit is configured to provide a signal of the third node to the pixel electrode under a control of the signal of the second node, the third node connecting the second control circuit and the second input circuit;
wherein a first terminal of the first control circuit is directly connected to the data line, a second terminal of the first control circuit is connected to the first gate line, and a third terminal of the first control circuit is connected to the first node;
a first terminal of the second control circuit is directly connected to a first terminal of the second input circuit, a second terminal of the second control circuit is connected to the second gate line, and a third terminal of the second control circuit is connected to the data line;
a first terminal of the first input circuit is connected to a third terminal of the second input circuit, a second terminal of the first input circuit is connected to the first node, and a third terminal of the first input circuit is connected to the reference signal terminal;
a second terminal of the second input circuit is connected to the second node; and
the first terminal of the first input circuit and the third terminal of the second input circuit are both connected to the pixel electrode.

2. The pixel circuit according to claim 1 , wherein a control terminal of the second control circuit is electrically connected to the second gate line, an input terminal of the second control circuit is electrically connected to the data line, and an output terminal of the second control circuit is electrically connected to the third node.

3. The pixel circuit according to claim 2 , wherein the second control circuit comprises: a first transistor, wherein
a gate of the first transistor is electrically connected to the second gate line, a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to the third node.

4. The pixel circuit according to claim 1 , wherein the first input circuit comprises a seventh transistor, a gate of the seventh transistor is electrically connected to the first node, a first electrode of the seventh transistor is electrically connected to the reference signal terminal, and a second electrode of the seventh transistor is electrically connected to the pixel electrode; and
the second input circuit comprises: an eighth transistor, a gate of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the third node, and a second electrode of the eighth transistor is electrically connected to the pixel electrode.

5. The pixel circuit according to claim 1 , wherein the first control circuit comprises: a second transistor, a gate of the second transistor is electrically connected to the first gate line, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the first node;
the latch circuit comprises: a third transistor, a fourth transistor, a fifth transistor and a sixth transistor;
a gate of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to a first voltage terminal, and a second electrode of the third transistor is electrically connected to the second node;
a gate of the fourth transistor is electrically connected to the first node, a first electrode of the fourth transistor is electrically connected to a second voltage terminal, and a second electrode of the fourth transistor is electrically connected to the second node;
a gate of the fifth transistor is electrically connected to the second node, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first node; and
a gate of the sixth transistor is electrically connected to the second node, a first electrode of the sixth transistor is electrically connected to the second voltage terminal, and a second electrode of the sixth transistor is electrically connected to the first node.

6. A method for driving the pixel circuit according to claim 1 , comprising: a first driving mode and a second driving mode;
in the first driving mode, loading a first level signal to the second gate line, loading a gate scanning signal to the first gate line, loading a data signal to the data line, and loading a first reference signal to the reference signal terminal, and
loading a second level signal to the second gate line, loading the first level signal to the first gate line, loading a second reference signal to the data line, and loading the first reference signal to the reference signal terminal; and
in the second driving mode, loading the second level signal to the first gate line, loading the first level signal to the second gate line, loading the first level signal to the data line, and loading the first reference signal to the reference signal terminal, and
loading the first level signal to the first gate line, loading the gate scanning signal to the second gate line, loading the data signal to the data line, and loading the first reference signal to the reference signal terminal.

7. A display panel, comprising: a plurality of first gate lines, a plurality of second gate lines, a plurality of data lines and a plurality of pixel cells arranged in an array; wherein each of the plurality of pixel cells comprises a plurality of sub-pixels, and each of the plurality of sub-pixels comprises a pixel circuit and a pixel electrode, one row of the plurality of sub-pixels correspond to one of the plurality of first gate lines and one of the plurality of second gate lines, and one column of the plurality of sub-pixels correspond to one of the plurality of data lines;
wherein the pixel circuit comprises a first control circuit, a latch circuit, a second control circuit, a first input circuit and a second input circuit; wherein
the first control circuit is configured to provide a signal on a data line to a first node under a control of a signal on a first gate line;
the latch circuit is configured to latch signals of the first node and a second node;
the second control circuit is configured to provide the signal on the data line to a third node under a control of a signal on a second gate line;
the first input circuit is configured to provide a signal of a reference signal terminal to a pixel electrode under a control of the signal of the first node; and
the second input circuit is configured to provide a signal of the third node to the pixel electrode under a control of the signal of the second node, the third node connecting the second control circuit and the second input circuit;
wherein a first terminal of the first control circuit is directly connected to the data line, a second terminal of the first control circuit is connected to the first gate line, and

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Jiguo
• Fan Jun

Classifications

• G09G3/3696 Primary

  Generation of voltages supplied to electrode drivers · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title