Pixel circuit, display module and driving method thereof

Patent metadata

Field	Value
Publication number	US-11615759-B2
Application number	US-202217832834-A
Country	US
Kind code	B2
Filing date	Jun 6, 2022
Priority date	Jan 16, 2019
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

The present disclosure relates to a pixel circuit. The pixel circuit may include a first pixel unit having a first display driving circuit, a first pixel, and a first control circuit, and a second pixel unit having a second display driving circuit, a second pixel electrode, and a second control circuit. The first control circuit may be configured to adjust and latch a voltage of a first positive phase node and the first display driving circuit. The first display driving circuit may be configured to provide a first display driving voltage to the first pixel electrode. The second control circuit may be configured to adjust and latch a voltage of a second positive phase node and the second display driving circuit. The second display driving circuit may be configured to provide a second display driving voltage to the second pixel electrode.

First claim

What is claimed is:

1. A pixel circuit comprising:
a first pixel unit, comprising a first display driving circuit, a first pixel electrode coupled to the first display driving circuit, and a first control circuit coupled to the first display driving circuit;
a second pixel unit, comprising a second display driving circuit, a second pixel electrode coupled to the second display driving circuit, and a second control circuit coupled to the second display driving circuit,
wherein the first display driving circuit and the second display driving circuit are coupled to a single display control line;
the first control circuit is configured to adjust and latch a voltage of a first positive phase node coupled to the first control circuit and the first display driving circuit, and the first display driving circuit is configured to provide a first display driving voltage to the first pixel electrode under control of a display control signal input by the display control line and the voltage of the first positive phase node;
the second control circuit is configured to adjust and latch a voltage of a second positive phase node coupled to the second control circuit and the second display driving circuit, and the second display driving circuit is configured to provide a second display driving voltage to the second pixel electrode under control of the display control signal and the voltage of the second positive phase node; and
the first display driving circuit and the second display driving circuit are coupled to one same data line.

2. The pixel circuit according to claim 1 , wherein the first control circuit and the second control circuit are mirrored on both sides of the display control line, and the first display driving circuit and the second display driving circuit are mirrored on both sides of the display control line.

3. The pixel circuit according to claim 1 , wherein the first pixel electrode comprises a first subpixel electrode and a second subpixel electrode coupled to each other, the first subpixel electrode, the second pixel electrode, and the second subpixel electrode are arranged in this order.

4. The pixel circuit according to claim 1 , wherein:
the first display driving circuit comprises a first data control subcircuit and a first display control subcircuit;
the first data control subcircuit is respectively coupled to the first positive phase node, a first inverting phase node coupled to the first display driving subcircuit and a first latch subcircuit, the data line, a black screen signal terminal, and a first display control node further coupled to the first display control subcircuit, and configured to control a connection between the first display control node and the black screen signal terminal under control of the first positive phase node and to control a connection between the first display control node and the data line under control of the first inverting phase node;
the first display control subcircuit is respectively coupled to the display control line, the first display control node and the first pixel electrode, and configured to control a voltage of the first pixel electrode according to a voltage of the first display control node under the control the display control signal input by the display control line.

5. The pixel circuit according to claim 4 , wherein the first display control subcircuit comprises a first display control transistor and a first storage capacitor, a control terminal of the first display control transistor is coupled to the display control line, a first terminal of the first display control transistor is coupled to the first display control node, a second terminal of the first display control transistor is coupled to a first terminal of the first storage capacitor.

6. The pixel circuit according to claim 4 , wherein:
the first control circuit comprises a first write control subcircuit and the first latch subcircuit coupled to the first write control subcircuit, the first write control subcircuit is configured to control a connection between the data line and the first positive phase node under control of a first write control line, and the first latch subcircuit is configured to latch the voltage of the first positive phase node, and control a voltage of the first inverting phase node according to the voltage of the first positive phase node.

7. The pixel circuit according to claim 6 , wherein the first write control subcircuit comprises a first write control transistor, a control terminal of the first write control transistor is coupled to the first write control line, a first terminal of the first write control transistor is coupled to the first positive phase node, and a second terminal of the first write control transistor is coupled to the data line.

8. The pixel circuit according to claim 6 , wherein:
the first latch subcircuit comprises a first inverting phase control circuit, a first inverting phase circuit, and a second inverting phase circuit;
the first inverting phase control circuit is respectively coupled to the first write control line, the first positive phase node, and a first control node further coupled to the second inverting phase circuit, and configured to control a connection between the first positive phase node and the first control node under the control of the first write control line;
the first inverting circuit is respectively coupled to the first positive phase node and the first inverting phase node, and configured to control the voltage of the first inverting node to be opposite phase to the voltage of the first positive phase node; and
the second inverting phase circuit is respectively coupled to the first control node and the first inverting phase node, and configured to control a voltage of the first control node to be opposite phase to the voltage of the first inverting phase node.

9. The pixel circuit according to claim 1 , wherein:
the second display driving circuit comprises a second data control subcircuit and a second display control subcircuit;
the second data control subcircuit is respectively coupled to the second positive phase node, a second inverting phase node coupled to the second display driving subcircuit and a second latch subcircuit, the data line, a black screen signal terminal and a second display control node further coupled to the second display control subcircuit, and configured to control a connection between the second display control node and the black screen signal terminal under the control of the second positive phase node and to control a connection between the second display control node and the data line under the control of the second inverting phase node; and
the second display control subcircuit is respectively coupled to the display control line, the second display control node and the second pixel electrode, and configured to control a voltage of the second pixel electrode according to a voltage of the second display control node under the control the display control signal input by the display control line.

10. The pixel circuit according to claim 9 , wherein the second display control subcircuit comprises a second display control transistor and a second storage capacitor, a control terminal of the second display control transistor is coupled to the display control line, a first terminal of the second display control transistor is coupled to the second display control node, a second terminal of the second display control transistor is coupled to a first terminal of the second storage capacitor.

11. The pixel circuit according to claim 9 , wherein:
the second control circuit comprises a second write control subcircuit and the second latch subcircuit coupled to the second write cont

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wang Jiguo
• Fan Jun
• Yang Xiaoyan
• Liu Yusheng

Classifications

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G3/3696 Primary

  Generation of voltages supplied to electrode drivers · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2310/0245

  Clearing or presetting the whole screen independently of waveforms, e.g. on power-on (G09G2310/063 takes precedence) · CPC title