Partial-fractional phase-locked loop with sigma delta modulator and finite impulse response filter

Patent metadata

Field	Value
Publication number	US-11955979-B2
Application number	US-202217835292-A
Country	US
Kind code	B2
Filing date	Jun 8, 2022
Priority date	Jun 8, 2022
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

First claim

What is claimed is:

1. Phase-locked loop circuitry comprising:
a phase frequency detector having a first input configured to receive a reference clock signal, a second input, and an output;
charge pump and loop filter circuitry having an input coupled to the output of the phase frequency detector and having an output;
a voltage-controlled oscillator having an input coupled to the output of the charge pump and loop filter circuitry and having an output;
a frequency divider having an input coupled to the output of the voltage-controlled oscillator and having an output coupled to the second input of the phase frequency detector;
a first order sigma delta modulator having an output, wherein the first order sigma delta modulator is non-dithered; and
a finite impulse response filter having an input coupled to the output of the first order sigma delta modulator and having an output coupled to the frequency divider.

2. The phase-locked loop circuitry of claim 1 , further comprising:
a multiplexer having a first input coupled to the output of the first order sigma delta modulator via a bypass path, a second input coupled to the output of the finite impulse response filter, and an output coupled to the frequency divider.

3. The phase-locked loop circuitry of claim 2 , further comprising:
a bit reduction circuit having an input coupled to the output of the finite impulse response filter and having an output coupled to the second input of the multiplexer, the bit reduction circuit being configured to drop one or more most significant bits from the output of the finite impulse response filter.

4. The phase-locked loop circuitry of claim 1 , further comprising:
a clipping circuit having an input coupled to the output of the first order sigma delta modulator and having an output coupled to the input of the finite impulse response filter, the clipping circuit being configured to keep a bitstream generated by the first order sigma delta modulator within a predetermined range of values.

5. The phase-locked loop circuitry of claim 1 , wherein the first order sigma delta modulator comprises:
a first summing circuit having first and second inputs and an output;
a quantizer having an input and an output;
a multiplier having an input coupled to the output of the quantizer and having an output;
a second summing circuit having a first input coupled to the output of the multiplier, a second input coupled to the output of the first summing circuit, and an output; and
a flip-flop having an input coupled to the output of the second summing circuit and having an output coupled to the second input of the first summing circuit.

6. The phase-locked loop circuitry of claim 1 , wherein the finite impulse response filter comprises:
a first flip-flop having an input and an output;
a second flip-flop having an input coupled to the output of the first flip-flop and having an output;
a third flip-flop having an input coupled to the output of the second flip-flop and having an output; and
a summing circuit having a first input coupled to the input of the first flip-flop, a second input coupled to the input of the second flip-flop, and a third input coupled to the input of the third flip-flop.

7. The phase-locked loop circuitry of claim 1 , wherein the finite impulse response filter comprises a three-tap or nine-tap finite impulse response filter configured to minimize a phase noise associated with the phase-locked loop circuitry.

8. The phase-locked loop circuitry of claim 1 , wherein the first order sigma delta modulator is configured to generate a periodic bitstream.

9. Phase-locked loop circuitry comprising:
a phase frequency detector having a first input configured to receive a reference clock signal, a second input, and an output;
charge pump and loop filter circuitry having an input coupled to the output of the phase frequency detector and having an output;
a voltage-controlled oscillator having an input coupled to the output of the charge pump and loop filter circuitry and having an output;
a frequency divider having an input coupled to the output of the voltage-controlled oscillator and having an output coupled to the second input of the phase frequency detector;
a first order sigma delta modulator having an output; and
a finite impulse response filter having:
an input coupled to the output of the first order sigma delta modulator;
an output coupled to the frequency divider;
a first flip-flop having an input coupled to the output of the first order sigma delta modulator and having an output;
a second flip-flop having an input coupled to the output of the first flip-flop and having an output; and
a first adder having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, and an output.

10. The phase-locked loop circuitry of claim 9 , wherein the finite impulse response filter further comprises:
a multiplier having a first input coupled to the output of the first adder, a second input configured to receive a filter coefficient, and an output.

11. The phase-locked loop circuitry of claim 9 , wherein the finite impulse response filter further comprises:
a third flip-flop having an input coupled to the output of the first flip-flop and having an output;
a fourth flip-flop having an input coupled to the output of the third flip-flop and having an output; and
a second adder having a first input coupled to the output of the third flip-flop, a second input coupled to the output of the fourth flip-flop, and an output.

12. The phase-locked loop circuitry of claim 11 , wherein the finite impulse response filter further comprises:
a first multiplier having a first input coupled to the output of the first adder, a second input configured to receive a first filter coefficient, and an output; and
a second multiplier having a first input coupled to the output of the second adder, a second input configured to receive a second filter coefficient, and an output.

13. The phase-locked loop circuitry of claim 12 , wherein the finite impulse response filter further comprises:
a third adder having a first input coupled to the output of the first multiplier, a second input coupled to the output of the second multiplier, and an output coupled to the frequency divider.

14. Circuitry comprising:
a phase frequency detector having a first input configured to receive a reference clock signal;
a frequency divider coupled between an output of the phase frequency detector and a second input of the phase frequency detector;
only one first order sigma delta modulator; and
a filter having an input coupled to an output of the first order sigma delta modulator and having an output coupled to the frequency divider.

15. The circuitry of claim 14 , wherein the first order sigma delta modulator is configured to generate a periodic bitstream.

16. The circuitry of claim 15 , wherein the filter comprises a finite impulse response filter configured to:
receive the periodic bitstream at its input; and
output a corresponding bitstream with a higher toggling frequency than the received periodic bitstream.

17. The circuitry of claim 14 , further comprising:
a multiplexer having a first input coupled to the output of the sigma delta modulator via a bypass path, a second input coupled to the output of the filter, and an output coupled to the frequency divider.

Assignees

• Apple Inc

Inventors

• Agarwal Reetika K
• Komijani Abbas
• Wang Hongrui

Classifications

• H03L7/0891 Primary

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03C3/0941

  applying frequency modulation at more than one point in the loop · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/185

  using a mixer in the loop (H03L7/187 - H03L7/195 take precedence) · CPC title