Dither-less error feedback fractional-n frequency synthesizer systems and methods

Patent metadata

Field	Value
Publication number	US-9450593-B2
Application number	US-201514952138-A
Country	US
Kind code	B2
Filing date	Nov 25, 2015
Priority date	Aug 20, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A fractional-N divider of a frequency synthesizer is driven by a dither-less error feedback modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. A first feedback loop generates the feedback signal. A second feedback loop disrupts fractional spurious tones and a third feedback loop provides approximately zero static error.

First claim

What is claimed is:

1. A delta sigma modulator configured to generate a cyclic output code, the delta sigma modulator comprising:
a combining circuit configured to combine an input signal, a phase-lock-loop (PLL) feedback signal provided by a divider circuit that is configured to divide a synthesized clock signal by the cyclic output code, and a modulator feedback signal to form a summed signal;
a quantizing circuit configured to quantize the summed signal to form the cyclic output code;
an amplifier configured to scale the cyclic output code to generate a scaled signal; and
a summing circuit configured to combine the summed signal, the cyclic output code, and the scaled signal to provide the modulator feedback signal.

2. The delta sigma modulator of claim 1 wherein the scaled signal introduces an error signal into the modulator feedback signal to disrupt tonal behavior due to the cyclic output code.

3. The delta sigma modulator of claim 1 further comprising a first filter configured to filter the scaled signal to generate a filtered signal, the summing circuit further configured to combine the filtered signal with the summed signal, the cyclic output code, and the scaled signal to provide the modulator feedback signal.

4. The delta sigma modulator of claim 3 wherein the filtered signal periodically cancels an error signal in the modulator feedback signal to reduce static error.

5. The delta sigma modulator of claim 1 wherein the combining circuit is in communication with the divider circuit, the quantizing circuit, and the summing circuit.

6. The delta sigma modulator of claim 1 wherein the amplifier is in communication with the quantizing circuit and the summing circuit.

7. The delta sigma modulator of claim 3 wherein the first filter is in communication with the amplifier and the summing circuit.

8. The delta sigma modulator of claim 3 further comprising a second filter in communication with the summing circuit and the combining circuit, the second filter configured to filter the modulator feedback signal.

9. A dither-less multi-stage noise shaping fractional-n frequency synthesizer including the delta sigma modulator of claim 1 .

10. A dither-less error feedback fractional-n frequency synthesizer including the delta sigma modulator of claim 1 .

11. A method to generate a cyclic output code, the method comprising:
combining an input signal, a phase-lock-loop (PLL) feedback signal provided by a divider circuit that is configured to divide a synthesized clock signal by the cyclic output code, and a modulator feedback signal to provide a summed signal;
quantizing the summed signal to provide the cyclic output code;
scaling the cyclic output code to provide a scaled signal; and
combining the summed signal, the cyclic output code, and the scaled signal to provide the modulator feedback signal.

12. The method of claim 11 wherein the scaled signal introduces an error signal into the modulator feedback signal to disrupt tonal behavior due to the cyclic output code.

13. The method of claim 11 further comprising filtering the scaled signal to provide a filtered signal.

14. The method of claim 13 wherein filtering the scaled signal includes delaying the scaled signal.

15. The method of claim 13 wherein the filtered signal is combined with the summed signal, the cyclic output code, and the scaled signal to provide the modulator feedback signal.

16. The method of claim 15 wherein the filtered signal periodically cancels an error signal in the modulator feedback signal to reduce static error.

17. The method of claim 11 further comprising filtering the modulator feedback signal before combining the input signal, the PLL feedback signal, and the modulator feedback signal.

18. A frequency synthesizer comprising:
a phase-lock-loop (PLL) circuit including a voltage controlled oscillator configured to generate a synthesized clock signal, a divider circuit configured to divide the synthesized clock signal by a cyclic output code to provide a PLL feedback signal, a phase frequency detector configured to compare the PLL feedback signal and a reference clock signal to generate a correction signal to adjust the synthesized clock signal; and
a delta sigma modulator configured to generate the cyclic output code, the delta sigma modulator including a combining circuit configured to combine an input signal, the PLL feedback signal, and a modulator feedback signal to provide a summed signal, a quantizing circuit configured to quantize the summed signal to provide the cyclic output code, a scaling circuit configured to scale the cyclic output code to provide a scaled signal, and a summing circuit configured to combine the summed signal, the cyclic output code, and the scaled signal to provide the modulator feedback signal.

19. The frequency synthesizer of claim 18 wherein the delta sigma modulator further includes a filter configured to filter the scaled signal to provide a filtered signal, the summing circuit further configured to combine the filtered signal with the summed signal, the cyclic output code, and the scaled signal to provide the modulator feedback signal.

20. A wireless device including the frequency synthesizer of claim 18 .

Assignees

• Skyworks Solutions Inc

Inventors

• Bourdi Tom Taoufik
• Obkircher Thomas
• Agarwal Bipul
• Mohan Chandra

Classifications

• H04L27/361

  Modulation using a single or unspecified number of carriers, e.g. with separate stages of phase and amplitude modulation · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03M7/3022 Primary

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title

• H04B2001/0491

  with frequency synthesizers, frequency converters or modulators · CPC title