Multi-channel multiplexer

Patent metadata

Field	Value
Publication number	US-11955964-B2
Application number	US-202117169638-A
Country	US
Kind code	B2
Filing date	Feb 8, 2021
Priority date	Dec 2, 2019
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.

First claim

What is claimed is:

1. A circuit comprising:
a plurality of inputs;
a plurality of switch assemblies including a first switch assembly, a second switch assembly, and a third switch assembly; and
a buffer including an input and an output,
wherein:
each of the plurality of switch assemblies includes:
a first switch coupled between a respective input of the plurality of inputs and an internal node;
a second switch coupled to the internal node; and
a third switch directly coupled to the internal node;

the input of the buffer is coupled to the respective second switches of the first, second, and third switch assemblies;
and
the output of the buffer is coupled to the respective third switches of the second and third switch assemblies instead of the first switch assembly.

2. The circuit of claim 1 , wherein the respective third switch of the first switch assembly is coupled to a ground node.

3. The circuit of claim 1 , wherein the buffer comprises a unity gain buffer.

4. The circuit of claim 1 , further comprising an operational amplifier that includes:
a first input coupled to the second switch of each of the plurality of switch assemblies;
a second input; and
an output.

5. The circuit of claim 4 , wherein the output of the operational amplifier is coupled to the second input of the operational amplifier.

6. The circuit of claim 4 , wherein the operation amplifier is configured as a unity gain buffer.

7. The circuit of claim 1 , wherein the plurality of switch assemblies are configured as a multiplexer.

8. The circuit of claim 7 , further comprising a multiplexer controller coupled to the respective first, second, and third switches of each of the plurality of switch assemblies.

9. A circuit comprising:
a plurality of inputs;
a multiplexer output node;
a plurality of switch assemblies including a first switch assembly, a second switch assembly, and a third switch assembly; and
a buffer including an input and an output,
wherein:
each of the plurality of switch assemblies includes:
a first switch coupled between a respective input of the plurality of inputs and an internal node;
a second switch coupled between the internal node and the multiplexer output node; and
a third switch directly coupled to the internal node;

the input of the buffer is coupled to the respective second switches of the first, second, and third switch assemblies; and
the output of the buffer is coupled to the respective third switches of the second and third switch assemblies instead of the first switch assembly.

10. The circuit of claim 9 , wherein the buffer comprises a unity gain buffer.

11. The circuit of claim 9 , further comprising an operational amplifier that includes:
a first input coupled to the multiplexer output node;
a second input; and
an output.

12. The circuit of claim 11 , wherein the output of the operational amplifier is coupled to the second input of the operational amplifier.

13. The circuit of claim 11 , wherein the operational amplifier is configured as a unity gain buffer.

14. The circuit of claim 9 , wherein the plurality of switch assemblies are configured as a multiplexer.

15. The circuit of claim 9 , further comprising a multiplexer controller coupled to the respective first, second, and third switches of each of the plurality of switch assemblies.

16. A circuit comprising:
a plurality of inputs;
a plurality of switch assemblies including a first switch assembly, a second switch assembly, and a third switch assembly; and
a buffer including an input and an output,
wherein:
each of the plurality of switch assemblies includes:
a first switch coupled between a respective input of the plurality of inputs and an internal node;
a second switch coupled to the internal node; and
a third switch coupled to the internal node;

the input of the buffer is coupled to the respective second switches of the first, second, and third switch assemblies;
and
the output of the buffer is coupled to the respective third switches of the second and third switch assemblies instead of the first switch assembly; and

an operational amplifier having a first input coupled to the respective second switch of each of the plurality of switch assemblies, a second input, and an output coupled to the second input.

17. The circuit of claim 16 , wherein the buffer comprises a unity gain buffer.

18. The circuit of claim 16 , wherein the respective first switch of each of the plurality switch assemblies is directly coupled to the respective input of the plurality of inputs.

Assignees

• Texas Instruments Inc

Inventors

• Agarwal Nitin
• Karanjkar Kunal Suresh
• R Venkata Ramanan

Classifications

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H03F3/72

  Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal · CPC title

• H03K17/005

  with several inputs only · CPC title

• H03K17/102

  in field-effect transistor switches · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title