Differential on-chip loop antenna

Patent metadata

Field	Value
Publication number	US-11955728-B2
Application number	US-202117381073-A
Country	US
Kind code	B2
Filing date	Jul 20, 2021
Priority date	Sep 27, 2017
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

Aspects of the embodiments are directed to an on-chip loop antenna and methods of manufacturing the same. In some embodiments, the on-chip loop antenna is in an integrated circuit (IC) die. The IC die comprises metal loops substantially centered around a core region of the IC die in a metallization stack of the IC die, a dielectric between spaces of the metal loops, an electric circuit in the core region electrically connected to the metal loops with an interconnect, and a ground plane in the metallization stack electrically connected to the loops with a first plurality of vias and to the electric circuit with a second plurality of vias. The first plurality of vias is different from the second plurality of vias, and the electric circuit includes an inductor. In some embodiments, the on-chip loop antenna can be carried by a semiconductor package.

First claim

What is claimed is:

1. An integrated circuit (IC) die, comprising:
metal loops substantially centered around a core region of the IC die;
a dielectric between spaces of the metal loops;
an electric circuit in the core region electrically coupled to the metal loops with an interconnect; and
a ground plane in a metallization stack of the IC die,
wherein:
the metal loops are in the metallization stack,
the ground plane is electrically coupled to the metal loops with a first plurality of vias,
the ground plane is electrically coupled to the electric circuit with a second plurality of vias,
the electric circuit includes an inductor,
the metal loops constitute a loop antenna,
exciting the metal loops in a first direction causes electric currents in the metal loops to cancel each other, and
exciting the metal loops in a second direction perpendicular to the first direction causes electric currents in the metal loops to aggregate.

2. The IC die of claim 1 , wherein the metal loops are electrically coupled together in series.

3. The IC die of claim 1 , wherein:
a portion of the electric circuit comprises a driver circuit configured to electromagnetically excite the metal loops,
the driver circuit has a first impedance,
the metal loops have a second impedance, and
the second impedance is substantially equal to the first impedance.

4. The IC die of claim 1 , wherein:
the interconnect has a first impedance,
the metal loops have a second impedance, and
the second impedance is substantially equal to the first impedance.

5. The IC die of claim 1 , wherein:
the metallization stack comprises layers of metal arranged along a thickness of the die, each layer separated from adjacent layers by the dielectric,
one of the metal loops is in a first layer of the metallization stack, and
another of the metal loops is in a second layer of the metallization stack different from the first layer.

6. The IC of claim 1 , wherein
the IC die comprises a plurality of loop antennas separated laterally from each other, and
each loop antenna surrounds a respective electric circuit.

7. The IC die of claim 6 , wherein the plurality of loop antennas laterally separated from each other are arranged in an array.

8. The IC die of claim 1 , wherein the metal loops comprise copper.

9. The IC die of claim 1 , wherein:
the metal loops are in a first plurality of layers of the metallization stack, and
the electric circuit is in a second plurality of layers of the metallization stack.

10. A semiconductor package, comprising:
a printed circuit board (PCB);
an IC die comprising:
a semiconductor substrate;
a metallization stack comprising layers of conductive metal traces stacked along a thickness of the IC die, separated from each other by a dielectric material, and electrically coupled with conductive vias in the dielectric material;
a ground plane in one of the layers of the metallization stack;
an IC including an inductor, a portion of the IC in the semiconductor substrate and another portion of the IC in the metallization stack, the IC being electrically coupled to the ground plane with one plurality of vias;
a loop antenna surrounding the IC in another one of the layers of the metallization stack and electrically coupled to the ground plane with another plurality of vias; and
a metal shield enclosing the IC die,
wherein the loop antenna includes metal loops configured to cause electric currents in the metal loops to cancel each other when excited in a first direction, and to aggregate when excited in a second direction perpendicular to the first direction.

11. The semiconductor package of claim 10 , wherein the IC die is coupled to the PCB with flip-chip interconnects.

12. The semiconductor package of claim 10 , wherein the metal shield comprises nickel-silver.

13. The semiconductor package of claim 10 , wherein the IC die and the metal shield are on one side of the PCB, and electromagnetic energy from the IC die radiates outwards through other sides of the PCB.

14. The semiconductor package of claim 10 , wherein the loop antenna comprises metal loops in a plurality of layers of the metallization stack, each metal loop stimulated by a respective antenna driver circuit in the IC.

15. The semiconductor package of claim 14 , wherein the metal loops are electrically coupled in series.

16. The semiconductor package of claim 10 , wherein:
the IC die further comprises a plurality of loop antennas,
each loop antenna is laterally separated from others in the plurality of loop antennas,
each loop antenna encloses a respective IC,
the ground plane is common to the plurality of loop antennas, and
the ground plane is in a space between the loop antennas.

17. The semiconductor package of claim 10 , wherein:
the IC die further comprises a plurality of loop antennas,
each loop antenna is laterally separated from others in the plurality of loop antennas, and
each loop antenna encloses a respective IC and a respective portion of the ground plane.

18. A computing device, comprising:
a memory;
a communications chip; and
an IC die that includes an antenna driver circuit having an inductor, wherein:
a loop antenna surrounds the antenna driver circuit,
an interconnect electrically couples the antenna driver circuit to the loop antenna,
a first plurality of vias through a metallization stack in the IC die electrically couples a ground plane with the antenna driver circuit,
a second plurality of vias through the metallization stack in the IC electrically couples the ground plane with the loop antenna,
the loop antenna includes metal loops configured to cause electric currents in the metal loops to cancel each other when excited in a first direction, and to aggregate when excited in a second direction perpendicular to the first direction.

19. The computing device of claim 18 , wherein the loop antenna comprises a plurality of metal loops in different layers of the metallization stack.

20. The computing device of claim 18 , wherein the loop antenna comprises a plurality of metal loops in a layer of the metallization stack.

Assignees

• Intel Corp

Inventors

• Weisman Nir
• Asaf Omer
• Goldberger Eyal

Classifications

• H10W44/248

  for antennas · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H01Q7/00 Primary

  Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop · CPC title

• H01L23/552

  Electricity · mapped topic