Semiconductor device and method for manufacturing semiconductor device

US11955562B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11955562-B2
Application numberUS-202217889597-A
CountryUS
Kind codeB2
Filing dateAug 17, 2022
Priority dateJul 6, 2018
Publication dateApr 9, 2024
Grant dateApr 9, 2024

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor device having a large on-state current and high reliability is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor over the second insulator. The fifth oxide is in contact with a top surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M, and Zn. The first oxide and the fifth oxide each contain at least one of constituent elements included in the second oxide. The third oxide and the fourth oxide each contain the element M. The third oxide and the fourth oxide include a region where the concentration of the element M is higher than that in the second oxide.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device comprising: a first insulator; a first oxide over the first insulator; a second oxide over and in contact with the first oxide; a first conductor over the second oxide; a second conductor over the second oxide; a second insulator covering the first oxide, the second oxide, the first conductor, and the second conductor; a third insulator over the second insulator; a third oxide over the second oxide, the third oxide being provided in an opening of the third insulator; a fourth insulator over the third oxide; and a third conductor over the third insulator, wherein the third oxide is in contact with a top surface of the second oxide, a first side surface of the first conductor and a first side surface of the second conductor, wherein the third oxide is in contact with a side surface of the third insulator in the opening, wherein the second oxide comprises In, an element M, and Zn, where the element M is Al, Ga, Y, or Sn, wherein the second insulator is in contact with a top surface of the first conductor, a top surface of the second conductor, a second side surface of the first conductor, a second side surface of the second conductor, a side surface of the second oxide, and a side surface of the first oxide, and wherein the third oxide comprises aluminum. 2. The semiconductor device according to claim 1 , wherein each of the first conductor and the second conductor comprises tantalum and nitrogen, and wherein the second insulator comprises aluminum and oxygen. 3. The semiconductor device according to claim 1 , wherein the first oxide comprises at least one of constituent elements included in the second oxide. 4. The semiconductor device according to claim 1 , wherein the second oxide has crystallinity. 5. A semiconductor device comprising: a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a first conductor over the third oxide; a second conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; a third conductor over the second insulator; a third insulator over the first conductor and the second conductor; and a fourth insulator over the third insulator, wherein the fifth oxide is in contact with a top surface of the second oxide, a first side surface of the first conductor, a first side surface of the second conductor, a first side surface of the third oxide, a first side surface of the fourth oxide, and a side surface of the third insulator, wherein the fifth oxide is in contact with an inner surface of an opening provided in the fourth insulator, wherein the third conductor is provided to fill the opening, wherein the second oxide comprises In, an element M and Zn, where the element M is Al, Ga, Y, or Sn, wherein the first oxide comprise at least one of constituent elements included in the second oxide, wherein the third oxide and the fourth oxide each comprise the element M, wherein the third oxide and the fourth oxide each comprise a region having a concentration of the element M higher than a concentration of the element M in the second oxide, and wherein the fifth oxide comprises aluminum. 6. The semiconductor device according to claim 5 , wherein each of the first conductor and the second conductor comprises tantalum and nitrogen, and wherein the second insulator comprises aluminum and oxygen. 7. The semiconductor device according to claim 5 , wherein the third oxide and the fourth oxide each comprise a region having a thickness of greater than or equal to 0.5 nm and less than or equal to 5 nm. 8. The semiconductor device according to claim 5 , wherein the third oxide and the fourth oxide each comprise a region having a thickness of greater than or equal to 1 nm and less than or equal to 3 nm. 9. The semiconductor device according to claim 5 , wherein the third oxide and the fourth oxide each comprise gallium. 10. The semiconductor device according to claim 5 , wherein the third oxide and the fourth oxide each have crystallinity. 11. A transistor device comprising: a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a first conductor over the third oxide; a second conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; a third conductor over the second insulator; a third insulator over the first conductor and the second conductor; and a fourth insulator over the third insulator, wherein the fifth oxide is in contact with a top surface of the second oxide, a first side surface of the first conductor, a first side surface of the second conductor, a first side surface of the third oxide, a first side surface of the fourth oxide, and a side surface of the third insulator, wherein the fifth oxide is in contact with an inner surface of an opening provided in the fourth insulator, wherein the third conductor is provided to fill the opening, wherein the second oxide comprises In, an element M and Zn, where the element M is Al, Ga, Y, or Sn, wherein the first oxide comprise at least one of constituent elements included in the second oxide, wherein the third oxide and the fourth oxide each comprise the element M, and wherein the third oxide and the fourth oxide each comprise a region having a concentration of the element M higher than a concentration of the element M in the second oxide, and wherein a shift voltage change amount ΔVsh of the transistor is less than or equal to 100 mV after 550 hours of the +GBT stress test, wherein a gate voltage of the +GBT stress test is set to 3.63V and a temperature of the +GBT stress test is set to 150° C. 12. The transistor according to claim 11 , wherein the shift voltage change amount ΔVsh of the transistor is less than or equal to 100 mV after 1100 hours of the +GBT stress test. 13. The transistor according to claim 11 , wherein each of the first conductor and the second conductor comprises tantalum and nitrogen, and wherein the second insulator comprises aluminum and oxygen. 14. The transistor according to claim 11 , wherein the third oxide and the fourth oxide each comprise a region having a thickness of greater than or equal to 0.5 nm and less than or equal to 5 nm. 15. The transistor according to claim 11 , wherein the third oxide and the fourth oxide each comprise a region having a thickness of greater than or equal to 1 nm and less than or equal to 3 nm. 16. The transistor according to claim 11 , wherein the third oxide and the fourth oxide each comprise gallium. 17. The transistor according to claim 11 , wherein the third oxide and the fourth oxide each have crystallinity. 18. The transistor according to claim 11 , wherein the fifth oxide comprises aluminum.

Assignees

Inventors

Classifications

  • Orientations of crystalline planes · CPC title

  • characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

  • having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

  • characterised by the materials · CPC title

  • Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11955562B2 cover?
A semiconductor device having a large on-state current and high reliability is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a s…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 09 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).