Passivation layers for thin film transistors and methods of fabrication

Patent metadata

Field	Value
Publication number	US-11955560-B2
Application number	US-202016914172-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Jun 26, 2020
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

First claim

What is claimed is:

1. A thin film transistor (TFT) structure, comprising:
a gate electrode;
a gate dielectric layer on the gate electrode;
a channel layer on the gate dielectric layer, wherein the channel layer comprises a semiconductor material with a first polarity and comprising a first metal and oxygen;
a multi-layer material stack on the channel layer, opposite the gate dielectric layer;
a dielectric material over the multi-layer material stack and beyond a sidewall of the channel layer; and
source and drain contacts through the dielectric material, and in contact with the channel layer, wherein the multi-layer material stack comprises:
a first layer in contact with the channel layer,
wherein the first layer comprises a second metal absent from the channel layer, and wherein the first layer has a second polarity, complementary to the first polarity; and
a second layer in contact with the first layer, wherein the second layer and the dielectric material have different compositions.

2. The TFT structure of claim 1 , wherein the second layer has n-type polarity and comprises In 2 O 3 , Ga 2 O 3 , ZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO or InMgZnO and wherein the semiconductor material has p-type polarity and comprises CuO x , NbO, NiO, SnO, Cu2O, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2, or ZnRh2O4.

3. The TFT structure of claim 1 , wherein the first layer has a thickness between 1 monolayer and 40 nm.

4. The TFT structure of claim 1 , wherein the second layer comprises Al 2 O 3 , AlN, HYO, SiO 2 , Y 2 O 3 , HfAlO x , AlSiO x , or AlSiN x .

5. The TFT structure of claim 1 , wherein the second layer has a higher permittivity than the dielectric material.

6. The TFT structure of claim 1 , wherein the second layer has a thickness between 3 nm and 5 nm.

7. The TFT structure of claim 1 , wherein the source and drain contacts are in contact with a sidewall of one of more material layers of the multi-layered material stack.

8. The TFT structure of claim 1 , wherein the multi-layered material stack further comprises a mask layer on the second layer, wherein the mask layer comprises a dielectric material different from a material of the second layer and the dielectric material.

9. The TFT structure of claim 1 , wherein the first layer a has p-type polarity and comprises CuO x , NbO, NiO, CoO, SnO, Cu2O, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2, or ZnRh2O4 and wherein the semiconductor material has n-type polarity and further comprises InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, or InMgZnO.

10. The TFT structure of claim 9 , wherein the semiconductor material further comprises Ti, W, Cu, Mn, Mg, Fe, Hf, Al, Ni, CO or Ru dopants, wherein the channel layer has a dopant concentration between e16 and e20, and wherein the semiconductor material comprises a thickness between 1 monolayer and 80 nm.

11. The TFT structure of claim 1 ,
further comprising
a third layer between the first layer and the second layer, wherein the third layer comprises a metal and oxygen.

12. The TFT structure of claim 11 , wherein the third layer has a thickness between one monolayer and 10 nm.

13. The TFT structure of claim 1 , wherein the second metal is Cu, Nb, Ni, Co, Sn, Cu, Ag, Al, Sc, Sr, B, P, La, Si, Se, Se, Rb, S, K, Na, Fe, Zn or Rh.

14. The TFT structure of claim 13 , wherein the semiconductor material comprises In and Zn, In and Ga, Ga and Zn, In and Al, In and Sn, In and Mg, Ga and Zn and Mg, Ga and Zn and Sn, Ga and Al and Zn, Ga and Al and Sn, Hf and Zn, Hf and In and Zn, Hf and Al and Ga and Zn, or In and Mg and Zn.

15. A system comprising:
a thin film transistor (TFT) structure, comprising:
a gate electrode;
a gate dielectric layer on the gate electrode;
a channel layer on the gate dielectric layer, wherein the channel layer comprises a semiconductor material with a first polarity and comprising a first metal and oxygen;
a multi-layer material stack on the channel layer, opposite the gate dielectric layer;
a dielectric material over the multi-layer material stack and beyond a sidewall of the channel layer;
a source and drain contacts through the dielectric material, and in contact with the channel layer, wherein the multi-layer material stack comprises:
a first layer comprising oxygen and a second metal, wherein the second metal is absent from the channel layer, wherein the first layer is in contact with the channel layer, and wherein the first layer has a second polarity, complementary to the first polarity; and
a second layer in contact with the first layer, wherein the second layer and the ILD dielectric material have a different composition; and

a memory element coupled with the drain contact.

16. The system of claim 15 , wherein the memory element is a magnetic tunnel junction device.

17. The system of claim 15 , wherein the memory element is a resistive random-access memory device.

18. A method of fabricating a transistor structure, the method comprising:
patterning an electrode material layer to form a gate electrode above a substrate;
depositing a gate dielectric layer on the gate electrode;
forming a material layer stack on the gate dielectric layer, the forming comprising:
depositing a channel layer on the gate dielectric layer;
depositing a barrier layer on the channel layer;
depositing an etch stop layer on the barrier layer;
depositing a sealant layer on the etch stop layer;
patterning the material layer stack into a block;
depositing a dielectric on the block;
patterning a plurality of openings in the block; and
forming metallization structures in the plurality of openings.

19. The method of claim 18 , wherein patterning the plurality of openings in the block comprises depositing a mask layer on the sealant layer and etching the mask layer, sealant layer, etch stop layer and the barrier layer to expose uppermost surface of the channel layer.

20. The method of claim 18 , wherein forming metallization structures comprises depositing one or more metals into the plurality of openings on onto an uppermost surface of the channel layer.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek A
• Sen Gupta Arnab
• Lajoie Travis W
• Atanasov Sarah
• Ku Chieh-Jen
• Sell Bernhard
• Sato Noriyuki
• Le Van
• Metz Matthew
• Yoo Hui Jae
• Wang Pei-Hua

Classifications

• H10D99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H01L29/7869 Primary

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H10B61/22

  of the field-effect transistor [FET] type · CPC title