Source or drain structures with high phosphorous dopant concentration

Patent metadata

Field	Value
Publication number	US-11955482-B2
Application number	US-202016876495-A
Country	US
Kind code	B2
Filing date	May 18, 2020
Priority date	May 18, 2020
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

Integrated circuit structures having high phosphorous dopant concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon and phosphorous, the phosphorous having an atomic concentration in a core region of the silicon greater than an atomic concentration in a peripheral region of the silicon.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack; and
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each of the epitaxial structures of the first and second source or drain structures comprising a core region of silicon and a peripheral region of silicon and having phosphorous therein, the phosphorous having an atomic concentration in the core region of silicon greater than an atomic concentration in the peripheral region of silicon, wherein the core region of silicon is laterally within and is on a bottom of the peripheral region of silicon, and wherein the core region of silicon has an uppermost surface at a same level as an uppermost surface of the peripheral region of silicon.

2. The integrated circuit structure of claim 1 , wherein the atomic concentration of phosphorous in the core region of silicon is greater than 5E21 atoms/cm 3 .

3. The integrated circuit structure of claim 1 , wherein the atomic concentration of phosphorous in the peripheral region of silicon is less than 4E21 atoms/cm 3 .

4. The integrated circuit structure of claim 1 , wherein the atomic concentration of phosphorous of the core region at the top of each of the epitaxial structures is greater than 6E21 atoms/cm 3 , and grades to less than 2E21 atoms/cm 3 in the peripheral region at a bottom of each of the epitaxial structures.

5. The integrated circuit structure of claim 1 , wherein the first and second source or drain structures have a resistivity of less than approximately 0.4 mOhm·cm.

6. The integrated circuit structure of claim 1 , wherein the lower fin portion includes a portion of an underlying bulk single crystalline silicon substrate.

7. The integrated circuit structure of claim 1 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

8. The integrated circuit structure of claim 1 , further comprising:
a first conductive contact on the epitaxial structure of the first source or drain structure; and
a second conductive contact on the epitaxial structure of the second source or drain structure.

9. The integrated circuit structure of claim 8 , wherein the first and second conductive contacts are in a partial recess in the epitaxial structures of the first and second source or drain structures, respectively.

10. An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer; and
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer, wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprising a core region of silicon and a peripheral region of silicon and having phosphorous therein, the phosphorous having an atomic concentration in the core region of silicon greater than an atomic concentration in the peripheral region of silicon, wherein the core region of silicon is laterally within and is on a bottom of the peripheral region of silicon, and wherein the core region of silicon has an uppermost surface at a same level as an uppermost surface of the peripheral region of silicon.

11. The integrated circuit structure of claim 10 , wherein the atomic concentration of phosphorous in the core region of silicon is greater than 5E21 atoms/cm 3 .

12. The integrated circuit structure of claim 10 , wherein the atomic concentration of phosphorous in the peripheral region of silicon is less than 4E21 atoms/cm 3 .

13. The integrated circuit structure of claim 10 , wherein the atomic concentration of phosphorous of the core region at the top of each of the epitaxial structures is greater than 6E21 atoms/cm 3 , and grades to less than 2E21 atoms/cm 3 in the peripheral region at a bottom of each of the epitaxial structures.

14. The integrated circuit structure of claim 10 , wherein the first and second source or drain structures have a resistivity of less than approximately 0.4 mOhm·cm.

15. The integrated circuit structure of claim 10 , wherein the lower fin portion includes a portion of an underlying bulk single crystalline silicon substrate.

16. The integrated circuit structure of claim 10 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

17. The integrated circuit structure of claim 10 , further comprising:
a first conductive contact on the capping semiconductor layer of the first source or drain structure; and
a second conductive contact on the capping semiconductor layer of the second source or drain structure.

18. The integrated circuit structure of claim 17 , wherein the first and second conductive contacts are in a partial recess in the capping semiconductor layers of the first and second source or drain structures, respectively.

19. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack; and
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each of the epitaxial structures of the first and second source or drain structures comprising a core region of silicon and a peripheral region of silicon and having phosphorous therein, the phosphorous having an atomic concentration in the core region of silicon greater than an atomic concentration in the peripheral region of silicon, wherein the core region of silicon is laterally within and is on a bottom of the peripheral region of silicon, and wherein the core region of silicon has an uppermost surface at a same level as an uppermost surface of the peripheral region of silicon.

20. The computing device of claim 19 , further comprising:
a memory coupled to the board.

21. The computing device of claim 19 , further comprising:
a communication chip coupled to the board.

22. The computing device of claim 19 , further comprising:
a camera coupled to the board.

23. The computing device of claim 19 , further comprising:
a battery coupled to the board.

24. The computing device of claim 19 , further comprising:
an antenna coupled to the board.

25. The computing device of claim 19 , wherein the

Assignees

• Intel Corp

Inventors

• Ehlert Robert
• Jen Timothy
• Badmaev Alexander
• Hegde Shridhar
• Charue-Bakker Sandrine

Classifications

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/013 Primary

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title