Semiconductor device and electronic system

Patent metadata

Field	Value
Publication number	US-11955470-B2
Application number	US-202117229062-A
Country	US
Kind code	B2
Filing date	Apr 13, 2021
Priority date	Sep 28, 2020
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

A semiconductor device includes a first peripheral circuit region comprising a plurality of lower circuitries, a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries, and a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction. The plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first peripheral circuit region comprising a plurality of lower circuitries;
a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries; and
a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction, such that a lower surface of the cell region is on an upper surface of the first peripheral circuit region and lower surface of the second peripheral circuit region is on an upper surface of the cell region,
wherein the plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.

2. The semiconductor device of claim 1 , wherein the cell region further comprises a first bonding metal pad,
the second peripheral circuit region further comprises a second bonding metal pad, and
the second word line connects to the first upper circuitry through a bonding structure comprising the first bonding metal pad and the second bonding metal pad.

3. The semiconductor device of claim 1 , wherein the cell region further comprises a cell substrate between the plurality of word lines and the first peripheral circuit region, and
the first word line connects to the first lower circuitry through a contact plug passing through the cell substrate.

4. The semiconductor device of claim 1 , wherein the first peripheral circuit region comprises a plurality of first transistors,
the second peripheral circuit region comprises a plurality of second transistors, and
an operating voltage of each of the plurality of first transistors is different from an operating voltage of each of the plurality of second transistors.

5. The semiconductor device of claim 1 , wherein the cell region further comprises a plurality of bit lines between the plurality of word lines and the second peripheral circuit region, and
the plurality of bit lines comprise a first bit line connected to a second lower circuitry that is selected from the plurality of lower circuitries and a second bit line connected to a second upper circuitry that is selected from the plurality of upper circuitries.

6. The semiconductor device of claim 1 , wherein the cell region comprises a first memory cell block and a second memory cell block, the first memory cell block including first structures, the second memory cell block including second structures different from the first structures, the first structures are apart from the second structures in a lateral direction,
the first memory cell block comprises a first gate stack comprising at least one first gate line connected to at least one lower circuitry selected from the plurality of lower circuitries, and
the second memory cell block comprises a second gate stack comprising at least one second gate line connected to at least one upper circuitry selected from the plurality of upper circuitries.

7. The semiconductor device of claim 1 , wherein the cell region further comprises a plurality of memory cell blocks and a plurality of first bonding metal pads,
each of plurality of the memory cell blocks comprises a gate stack comprising a plurality of gate lines,
the second peripheral circuit region further comprises a plurality of second bonding metal pads,
each of the plurality of gate lines included in a first memory cell block selected from the plurality of memory cell blocks connects to the first peripheral circuit region through a contact structure comprising a contact plug that passes through at least one of the plurality of gate lines, and
each of the plurality of gate lines included in a second memory cell block selected from the plurality of memory cell blocks connects to the second peripheral circuit region through a plurality of bonding structures including the plurality of first bonding metal pads and the plurality of second bonding metal pads.

8. The semiconductor device of claim 1 , wherein the cell region comprises:
a conductive plate between the first peripheral circuit region and the plurality of word lines; and
a common source line contact plug extending in the vertical direction from the conductive plate toward the second peripheral circuit region, the common source line contact plug connecting to one circuitry selected from the plurality of upper circuitries.

9. The semiconductor device of claim 1 , wherein the cell region further comprises a connection contact plug extending in the vertical direction at a position apart from the plurality of word lines in a lateral direction,
one end of the connection contact plug connects to one upper circuitry selected from the plurality of upper circuitries, and another end of the connection contact plug extends into the first peripheral circuit region and connects to one lower circuitry selected from the plurality of lower circuitries.

10. A semiconductor device comprising:
a first peripheral circuit region comprising a first peripheral circuit substrate, a plurality of lower circuitries, and a plurality of lower conductive lines;
a cell region comprising a cell substrate on the first peripheral circuit region, a plurality of gate lines on the cell substrate, a plurality of conductive pad regions connected to the plurality of gate lines, and a plurality of first bonding metal pads; and
a second peripheral circuit region apart from the first peripheral circuit region with the cell region between the first peripheral circuit and the second peripheral circuit region, such that a lower surface of the cell region is on an upper surface of the first peripheral circuit region and lower surface of the second peripheral circuit region is on an upper surface of the cell region, the second peripheral circuit region comprising (A) a second peripheral circuit substrate, (B) a plurality of upper circuitries, (C) a plurality of upper conductive lines, and (D) a plurality of second bonding metal pads bonded to the plurality of first bonding metal pads,
wherein the plurality of gate lines comprise (A) a first gate line connected to a first lower circuitry selected from the plurality of lower circuitries and (B) a second gate line connected to a first upper circuitry selected from the plurality of upper circuitries.

11. The semiconductor device of claim 10 , wherein the cell region further comprises a contact plug extending in a vertical direction from a first conductive pad region toward the second peripheral circuit region, the first conductive pad region selected from the plurality of conductive pad regions, and
the second gate line connects to a first upper conductive line selected from the plurality of upper conductive lines through the first conductive pad region, the contact plug, and one first bonding metal pad selected from the plurality of first bonding metal pads.

12. The semiconductor device of claim 10 , wherein the cell region comprises a second contact structure passing through the cell substrate and extending into the first peripheral circuit region, and
the first gate line connects to a first lower conductive line through the second contact structure, the first lower conductive line selected from the plurality of lower conductive lines.

13. The semiconductor device of claim 10 , wherein the cell region comprises a first contact structure and a second contact structure,
the first contact structure comprises a contact plug

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jiwon
• Ahn Jaeho
• Hwang Sungmin
• Lim Joonsung
• Sung Sukkang

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/874

  On different surfaces · CPC title