Semiconductor device package comprising a pin in the form of a drilling screw

Patent metadata

Field	Value
Publication number	US-11955415-B2
Application number	US-202117359824-A
Country	US
Kind code	B2
Filing date	Jun 28, 2021
Priority date	Jul 3, 2020
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

The semiconductor device package comprises a die carrier, at least one semiconductor die disposed on the carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier, an encapsulant disposed above the semiconductor die, an electrical connector electrically connected with the contact pad, a drilling screw screwed through the encapsulant and connected with the electrical connector.

First claim

The invention claimed is:

1. A semiconductor device package, comprising:
a die carrier;
at least one semiconductor die disposed on the die carrier;
an encapsulant disposed above the semiconductor die;
an electrical connector electrically connected with the semiconductor die or with another electrical device; and
a metallic drilling screw screwed through the encapsulant and connected with the electrical connector, wherein an outer end of the metallic drilling screw extends through a first upper main face of the encapsulant opposite from the die carrier.

2. The semiconductor device package according to claim 1 , wherein the drilling screw is drilled into the electrical connector.

3. The semiconductor device package according to claim 1 , wherein the drilling screw comprises a drilling end section, a screw section adjacent to the drilling end section, and a rod-shaped section adjacent to the screw section.

4. The semiconductor device package according to claim 3 , wherein
the drilling screw further comprises a driver section, wherein the driver section is either located at an end of the rod-shaped section or integrated in the end of the rod-shaped section.

5. The semiconductor device package according to claim 1 , further comprising
a substrate, wherein the substrate comprises the carrier and is one out of a group consisting of a leadframe, a direct copper bonded substrate, a direct aluminum bonded substrate, and an active metal brazing substrate.

6. The semiconductor device package according to claim 5 , wherein the substrate is one out of a group consisting of a direct copper bonded substrate, a direct aluminum bonded substrate, or an active metal brazing substrate, wherein the substrate comprises a ceramic layer, in particular one or more of AlO, AlN, Al 2 O 3 , or a dielectric layer, in particular Si 3 N 4 .

7. The semiconductor device package according to claim 1 , wherein
the electrical connector is one out of a group consisting of:
a sleeve comprising an inner cavity,
a metal block, and
a metal layer of one of a direct copper bonded substrate, a direct aluminum bonded substrate, or an active metal brazing substrate.

8. The semiconductor device package according to claim 1 , wherein the drilling screw is made by one of Cu, a Cu alloy, an Al alloy, or steel.

9. The semiconductor device package according to claim 1 , further comprising
a plurality of semiconductor transistor dies disposed on the carrier, at least one of the semiconductor transistor dies comprising at least one contact pad;
a plurality of semiconductor diode dies disposed on the die carrier, wherein at least one of the semiconductor diode dies is connected in parallel with one of the semiconductor transistor dies;
a plurality of electrical connectors, wherein at least one of the electrical connectors is connected with one of the contact pads of the semiconductor transistor dies; and
a plurality of metallic drilling screws, wherein at least one of the metallic drilling screws is screwed through the encapsulant and connected with the electrical connector.

10. The semiconductor device package according to claim 9 , wherein the semiconductor transistor dies and the semiconductor diode dies are interconnected to form an AC/AC converter circuit, an AC/DC converter circuit, a DC/AC converter circuit, a frequency converter or a DC/DC converter circuit.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Scharf Thorsten
• Bemmerl Thomas
• Gruber Martin
• Meyer Thorsten
• Singer Frank

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/127

  characterised by arrangements for sealing or adhesion · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title