Memory device and method of reading data

Patent metadata

Field	Value
Publication number	US-11955183-B2
Application number	US-202217827852-A
Country	US
Kind code	B2
Filing date	May 30, 2022
Priority date	Sep 20, 2018
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

First claim

What is claimed is:

1. A non-volatile memory, comprising:
a memory cell region extending in a first horizontal direction and bounded on a first end by a first word line cut and bounded on a second end opposite the first end by a second word line cut;
a plurality of inner memory cell strings including first memory cells of the memory cell region that are connected to a plurality of inner pillars extending vertically upward through an inner region of the memory cell region;
a plurality of outer memory cell strings including second memory cells of the memory cell region that are connected to a plurality of outer pillars extending vertically upward through an outer region of the memory cell region, the outer region being adjacent to the first and second word line cuts than the inner region;
a plurality of first bit lines connected to the inner pillars and extending in a second horizontal direction crossing the first horizontal direction;
a plurality of second bit lines connected to the outer pillars and extending in the second horizontal direction;
a first page buffer circuit connected to the first bit lines and including a first latch storing data on the first memory cells based on a first read level voltage and a second latch storing data on the first memory cells based on a second read level voltage different from the first read level voltage; and
a second page buffer circuit connected to the second bit lines and including a third latch storing data on the second memory cells based on the first read level voltage and a fourth latch storing data on the second memory cells based on the second read level voltage,
wherein the first page buffer circuit is configured to output a first read data of the first memory cells using the first latch, and the second page buffer circuit is configured to output a second read data of the second memory cells using the fourth latch.

2. The non-volatile memory of claim 1 , wherein the first word line cut and the second word line cut extend in the first horizontal direction.

3. The non-volatile memory of claim 1 , wherein a first distance between the inner memory cell strings and the first word line cut is larger than a second distance between the outer memory cell strings and the first word line cut, and
a third distance between the inner memory cell strings and the second word line cut is larger than a fourth distance between the outer memory cell strings and the second word line cut.

4. The non-volatile memory of claim 1 , wherein the first page buffer circuit further includes a fifth latch storing data on the first memory cells based on a third read level voltage different from the first and second read level voltages, and
the second page buffer circuit further includes a sixth latch storing data on the second memory cells based on the third read level voltage.

5. The non-volatile memory of claim 4 , wherein the first page buffer circuit further includes a seventh latch storing the first read data from the first latch and the first page buffer circuit is further configured to output the first read data using the seventh latch, and
the second page buffer circuit further includes an eighth latch storing the second read data from the fourth latch and the second page buffer circuit is further configured to output the second read data using the eighth latch.

6. The non-volatile memory of claim 4 , wherein the second page buffer circuit is further configured to output the second read data of the second memory cells using one of the fourth latch and the sixth latch.

7. The non-volatile memory of claim 1 , further comprising:
a data input/output (I/O) circuit including the first and second page buffer circuits,
wherein the data I/O circuit performs a first mass bit counting for the data in the first latch and the data in the second latch, and a second mass bit counting for the data in the third latch and the data in the fourth latch.

8. The non-volatile memory of claim 7 , wherein the data I/O circuit outputs the first read data based on the first mass bit counting and the second read data based on the second mass bit counting.

9. The non-volatile memory of claim 1 , wherein the first bit lines include a third bit line and a fourth bit line, and
the first page buffer circuit includes a third page buffer connected to the third bit line and a fourth page buffer connected to the fourth bit line.

10. The non-volatile memory of claim 9 , wherein the second bit lines include a fifth bit line and a sixth bit line, and
the second page buffer circuit includes a fifth page buffer connected to the fifth bit line and a sixth page buffer connected to the sixth bit line.

11. A non-volatile memory, comprising:
a memory cell region extending in a first horizontal direction and bounded on a first end by a first word line cut and bounded on a second end opposite the first end by a second word line cut;
a plurality of inner memory cell strings including first memory cells of the memory cell region that are connected to a plurality of inner pillars extending vertically upward through an inner region of the memory cell region;
a plurality of outer memory cell strings including second memory cells of the memory cell region that are connected to a plurality of outer pillars extending vertically upward through an outer region of the memory cell region, the outer region being adjacent to the first and second word line cuts than the inner region;
a plurality of first bit lines connected to the inner pillars and extending in a second horizontal direction crossing the first horizontal direction;
a plurality of second bit lines connected to the outer pillars and extending in the second horizontal direction;
a first page buffer circuit connected to the first bit lines and including a first latch storing data on the first memory cells using a first read method and a second latch storing data on the first memory cells using a second read method different from the first read method; and
a second page buffer circuit connected to the second bit lines and including a third latch storing data on the second memory cells using the first read method and a fourth latch storing data on the second memory cells using the second read method,
wherein the first page buffer circuit is configured to select data in the first latch and output the data in the first latch as a first read data of the first memory cells, and
the second page buffer circuit is configured to select data in the fourth latch and output the data in the fourth latch as a second read data of the second memory cells.

12. The non-volatile memory of claim 11 , wherein the first word line cut and the second word line cut extend in the first horizontal direction.

13. The non-volatile memory of claim 11 , wherein the first page buffer circuit is configured to
perform a first read on the first memory cells using a first read level voltage and store a first result of the first reading into the first latch, and
perform a second read on the first memory cells using a second read level voltage different from the first read level voltage and store a second result of the second reading into the second latch, and
wherein the second page buffer circuit is configured to
perform a third read on the second memory cells using the first read level voltage and store a third result of the third reading into the third latch, and
perform a fourth read on the second memory cells using the second read level voltage and store a fourth result of the fourth reading into the fourth latch.

14. The non-volatile memory of claim 11 , wherein the first page buffer circuit further includes a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Su Chang
• Kim Seung Bum
• Lee Ji Young

Classifications

• G11C16/24 Primary

  Bit-line control circuits · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title