Memory system and method of operating the same

Patent metadata

Field	Value
Publication number	US-11955181-B2
Application number	US-202117551694-A
Country	US
Kind code	B2
Filing date	Dec 15, 2021
Priority date	Aug 3, 2021
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

A memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of string groups respectively connected to a corresponding select line, among a plurality of select lines. The peripheral circuit performs a program operation of data on the memory block. The control logic controls the program operation of the peripheral circuit. The memory block is connected to first to n-th word lines. The control logic is configured to control the peripheral circuit to perform a first program operation on a physical page, among physical pages that are included in a first string group, connected to an i-th word line, performs a second program operation on a physical page that is connected to an (i−1)-th word line, and perform a dummy program operation on a physical page that is connected to an (i+1)-th word line. Here, n is a natural number equal to or greater than 3, and i is a natural number greater than 0 and less than n−1.

First claim

What is claimed is:

1. A memory device comprising:
a memory block including a plurality of string groups respectively connected to a corresponding select line, among a plurality of select lines;
a peripheral circuit configured to perform a first program operation and a second program operation on the memory block; and
a control logic configured to control the program operation of the peripheral circuit,
wherein the memory block is connected to first to n-th word lines,
wherein the control logic is configured to control the peripheral circuit to perform the first program operation on a physical page, among a plurality of physical pages that are included in a first string group, connected to the i-th word line, perform the second program operation on a physical page that is connected to the (i−1)-th word line, perform the first program operation on a physical page, among a plurality of physical pages that are included in a second string group, connected to the (i+1)-th word line, perform a dummy program operation on a physical page, among the plurality of physical pages that are included in the first string group, connected to the (i+1)-th word line, perform the second program operation on the physical page that is connected to the i-th word line, perform the dummy program operation on a physical page, among the plurality of physical pages that are included in the second string group, connected to the (i+1)-th word line, and perform the second program operation on the physical page that is connected to the i-th word line, and
wherein n is a natural number equal to or greater than 3, and i is a natural number greater than 0 and less than n−1.

2. The memory device of claim 1 , wherein the first program operation is an operation of programming a threshold voltage of a memory cell to a first target level, and
wherein the second program operation is an operation of programming the threshold voltage of the memory cell to a second target level.

3. The memory device of claim 2 , wherein the first target level is a level that is lower than the second target level.

4. The memory device of claim 3 , wherein the control logic is configured to control the peripheral circuit to perform the second program operation on the physical page that is connected to the i-th word line after performing the dummy program operation on the physical page that is connected to the (i+1)-th word line.

5. The memory device of claim 4 , wherein the control logic is configured to control the peripheral circuit to perform the first program operation on a physical page that is connected to an (i+2)-th word line after performing the second program operation on the physical page that is connected to the i-th word line.

6. The memory device of claim 1 , wherein the control logic controls the peripheral circuit to sequentially perform the first program operation on physical pages, among the plurality of physical pages that are included in the first string group and the second string group, connected to an (i+2)-th word line, after performing the second program operation on the physical, among the plurality of physical pages that are included in the second string group, page connected to the i-th word line.

7. The memory device of claim 1 , wherein the control logic controls the peripheral circuit to sequentially perform the first program operation on physical pages, among a plurality of physical pages that are included in the first string group and a second string group, connected to the i-th word line, sequentially perform the second program operation on physical pages, among the plurality of physical pages that are included in the first string group and the second string group, connected to the (i−1)-th word line, sequentially perform the dummy program operation on physical pages, among the plurality of physical pages that are included in the first string group and the second string group, connected to the (i+1)-th word line, and sequentially perform the second program operation on physical pages, among the plurality of physical pages that are included in the first string group and the second string group, connected to the i-th word line.

8. The memory device of claim 7 , wherein the control logic controls the peripheral circuit to sequentially perform the first program operation on physical pages, among the plurality of physical pages that are included in the first string group and the second string group, connected to an (i+2)-th word line, after sequentially performing the second program operation on the physical pages, among the plurality of physical pages that are included in the first string group and the second string group, connected to the i-th word line.

9. A method of operating a memory system that performs a first program operation and a second program operation on a memory block including a plurality of string groups respectively connected to a corresponding select line, among a plurality of select lines and wherein the memory block is connected to first to n-th word lines, the method comprising:
performing a first program operation on a memory cell connected to an i-th word line among memory cells included in a first string group and performing a second program operation on a memory cell connected to an (i−1)-th word line among the memory cells included in a first string group;
performing the first program operation on a memory cell connected to the i-th word line among memory cells included in a second string group and performing the second program operation on a memory cell connected to the (i−1)-th word line among the memory cells included in the second string group; and
performing a dummy program operation on a memory cell connected to an (i+1)-th word line among the memory cells included in the first string group,
wherein i is a natural number greater than 2.

10. The method of claim 9 , wherein the first program operation is an operation of programming a threshold voltage of a memory cell to a first target level, and
wherein the second program operation is an operation of programming the threshold voltage of the memory cell to a second target level.

11. The method of claim 10 , wherein the first target level is a level that is lower than the second target level.

12. The method of claim 9 , further comprising:
performing the dummy program operation on a memory cell connected to an (i+1)-th word line among the memory cells included in the second string group, after performing the dummy program operation on the memory cell connected to the (i+1)-th word line among the memory cells included in the second string group.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title