Invisible scan architecture for secure testing of digital designs

Patent metadata

Field	Value
Publication number	US-11953548-B2
Application number	US-202318152209-A
Country	US
Kind code	B2
Filing date	Jan 10, 2023
Priority date	Jan 14, 2022
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality. Specific sequences of key patterns cause the design to transition into a test mode or a normal mode.

First claim

The invention claimed is:

1. A computer-implemented method comprising:
receiving one or more key patterns for testing a design of a hardware intellectual property (IP), wherein (a) the design comprises one or more invisible scan chains and (b) each invisible scan chain comprises a plurality of flip-flops connected on-demand upon verification of the one or more key patterns;
determining a mode for the design based at least in part on the one or more key patterns and using a scan enable finite state machine (SEFSM);
responsive to determining a test mode for the design:
loading a set of scan input data into the one or more invisible scan chains of the design over a first configurable number of clock cycles;
causing the design to perform a normal operation for a second configurable number of clock cycles; and
obtaining a set of scan output data from the one or more invisible scan chains of the design over the first configurable number of clock cycles; and

performing one or more automated actions based at least in part on whether the set of scan output data is in accordance with an expected set of scan output data.

2. The method of claim 1 , wherein the SEFSM is realized within the design using a plurality of invisible scan flip-flops present in the design.

3. The method of claim 2 , wherein the one or more invisible scan chains comprise a plurality of original flip-flops different than the plurality of invisible scan flip-flops.

4. The method of claim 3 , wherein the plurality of original flip-flops is used by the design to perform the normal operation.

5. The method of claim 1 , wherein each of the one or more invisible scan chains is associated with a configurable scan path spanning a plurality of original flip-flops.

6. The method of claim 1 , the method further comprising:
modifying the configurable scan path of a particular invisible scan chain based at least in part on identifying a second plurality of original flip-flops present in the design.

7. The method of claim 1 , wherein the set of scan input data is loaded into each flip-flop of the one or more invisible scan chains in a first-in first-out (FIFO) manner.

8. The method of claim 1 , wherein the mode for the design is determined further based at least in part on a particular sequence with which the one or more key patterns are received.

9. A system comprising one or more processors, a memory, and one or more programs stored in the memory, the one or more programs comprising instructions configured to cause the one or more processors to:
receive one or more key patterns for testing a design of a hardware intellectual property (IP), wherein (a) the design comprises one or more invisible scan chains and (b) each invisible scan chain comprises a plurality of flip-flops connected on-demand upon verification of the one or more key patterns;
determine a mode for the design based at least in part on the one or more key patterns and using a scan enable finite state machine (SEFSM);
responsive to determining a test mode for the design:
load a set of scan input data into the one or more invisible scan chains of the design over a first configurable number of clock cycles;
cause the design to perform a normal operation for a second configurable number of clock cycles; and
obtain a set of scan output data from the one or more invisible scan chains of the design over the first configurable number of clock cycles; and

perform one or more automated actions based at least in part on whether the set of scan output data is in accordance with an expected set of scan output data.

10. The system of claim 9 , wherein the SEFSM is realized within the design using a plurality of invisible scan flip-flops present in the design.

11. The system of claim 10 , wherein the one or more invisible scan chains comprise a plurality of original flip-flops different than the plurality of invisible scan flip-flops.

12. The system of claim 11 , wherein the plurality of original flip-flops is used by the design to perform the normal operation.

13. The system of claim 9 , wherein each of the one or more invisible scan chains is associated with a configurable scan path spanning a plurality of original flip-flops.

14. The system of claim 9 , the one or more programs comprising instructions configured to further cause the one or more processors to:
modify the configurable scan path of a particular invisible scan chain based at least in part on identifying a second plurality of original flip-flops present in the design.

15. The system of claim 9 , wherein the set of scan input data is loaded into each flip-flop of the one or more invisible scan chains in a first-in first-out (FIFO) manner.

16. The system of claim 9 , wherein the mode for the design is determined further based at least in part on a particular sequence with which the one or more key patterns are received.

17. An apparatus, the apparatus comprising at least one processor and at least one memory, the at least one memory having computer-coded instructions therein, wherein the computer-coded instructions are configured to, in execution with the at least one processor, cause the apparatus to:
receive one or more key patterns for testing a design of a hardware intellectual property (IP), wherein (a) the design comprises one or more invisible scan chains and (b) each invisible scan chain comprises a plurality of flip-flops connected on-demand upon verification of the one or more key patterns;
determine a mode for the design based at least in part on the one or more key patterns and using a scan enable finite state machine (SEFSM);
responsive to determining a test mode for the design:
load a set of scan input data into the one or more invisible scan chains of the design over a first configurable number of clock cycles;
cause the design to perform a normal operation for a second configurable number of clock cycles; and
obtain a set of scan output data from the one or more invisible scan chains of the design over the first configurable number of clock cycles; and

perform one or more automated actions based at least in part on whether the set of scan output data is in accordance with an expected set of scan output data.

18. The apparatus of claim 17 , wherein the SEFSM is realized within the design using a plurality of invisible scan flip-flops present in the design.

19. The apparatus of claim 18 , wherein the one or more invisible scan chains comprise a plurality of original flip-flops different than the plurality of invisible scan flip-flops.

20. The apparatus of claim 19 , wherein the plurality of original flip-flops is used by the design to perform the normal operation.

Assignees

• Univ Florida

Inventors

• Bhunia Swarup
• Gaikwad Pravin Dasharth
• Cruz Jonathan William
• Paria Sudipta

Classifications

• G01R31/318536 Primary

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title

• G01R31/31719

  Security aspects, e.g. preventing unauthorised access during test · CPC title

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G01R31/318588

  Security aspects · CPC title

• G06F2115/08

  Intellectual property [IP] blocks or IP cores · CPC title