End-to-end data protection for far memory data transfer from host to media

Patent metadata

Field	Value
Publication number	US-11947995-B2
Application number	US-202016878064-A
Country	US
Kind code	B2
Filing date	May 19, 2020
Priority date	May 19, 2020
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.

First claim

What is claimed is:

1. A memory device comprising:
a nonvolatile memory (NVM) media having a media write unit as a smallest writeable unit of the NVM media, where the media write unit is different in size than a host write unit of a host controller to be coupled to the memory device; and
a media controller to receive write data in a transaction layer message of a protocol for a write transaction from the host controller when coupled, and send an acknowledgement transaction layer message of the protocol to the host controller to indicate specific media write units of the write data for the write transaction successfully committed to the NVM media.

2. The memory device of claim 1 , wherein the media write unit comprises a data slice and the host write unit comprises a data sector, wherein the data slice includes a multiple of data sectors.

3. The memory device of claim 1 , wherein the media controller is to receive the write data and an associated commit indicator to indicate whether the write data is to be committed to the NVM media even if an amount of received write data does not equal a size of the media write unit.

4. The memory device of claim 1 , wherein the media controller is to maintain write credits to indicate an available number of writes that can be pending to the NVM media.

5. The memory device of claim 4 , wherein the media controller is to decrement the write credits in response to receive of the write transaction, and increment the write credits in response to successfully committing write data to the NVM media.

6. The memory device of claim 4 , wherein each of the write credits is to indicate multiple write operations to the NVM media.

7. The memory device of claim 6 , wherein the media controller is to receive a configuration command from the host controller to set a number of write credits and a number of media write units per write credit.

8. The memory device of claim 1 , wherein the acknowledgement transaction layer message is to indicate errors per host write unit of the media write unit for the write data.

9. The memory device of claim 1 , further comprising:
a peripheral component interconnection express (PCIe) link controller to couple to the host controller over a PCIe link, wherein the protocol comprises PCIe;
wherein the media controller is to receive the write transaction and send the acknowledgement transaction layer message over the PCIe link.

10. The memory device of claim 9 , wherein the acknowledgement transaction layer message comprises a vendor defined message (VDM).

11. The memory device of claim 9 , wherein the acknowledgement transaction layer message comprises a transaction layer packet (TLP) of a transaction layer of the PCIe link.

12. The memory device of claim 1 , wherein the write transaction is to indicate a last host write unit for the write transaction.

13. A system, comprising:
a host controller to write data in host write units as a smallest writeable unit for the host controller; and
a nonvolatile memory (NVM) device, including
a nonvolatile memory (NVM) media having a media write unit as a smallest writeable unit of the NVM media, where the media write unit is different in size than a host write unit of the host controller; and
a media controller to receive write data in a transaction layer message of a protocol for a write transaction from the host controller when coupled, and send an acknowledgement transaction layer message of the protocol to the host controller to indicate specific media write units of the write data for the write transaction successfully committed to the NVM media.

14. The system of claim 13 , wherein the media controller is to maintain write credits to indicate an available number of writes that can be pending to the NVM media.

15. The system of claim 13 , wherein the acknowledgement transaction layer message is to indicate errors per host write unit of the media write unit for the write data.

16. The system of claim 13 , the NVM device further comprising:
a peripheral component interconnection express (PCIe) link controller to couple to the host controller over a PCIe link, wherein the protocol is PCIe;
wherein the media controller is to receive the write transaction and send the acknowledgement transaction layer message over the PCIe link.

17. The system of claim 13 , wherein the write transaction is to indicate a last host write unit for the write transaction.

18. The system of claim 13 , further comprising one or more of:
a host processor device coupled to the host controller;
a display communicatively coupled to a host processor;
a network interface communicatively coupled to a host processor; or
a battery to power the system.

19. A method for writing data, comprising:
receiving a write transaction at a media controller from a host controller, the write transaction including multiple host write units of write data, wherein the media controller is to commit data to a nonvolatile memory (NVM) media in media write units, wherein a single media write unit includes multiple host write units;
committing the write data to the NVM media; and
sending an acknowledgement transaction layer message of a protocol to the host controller to indicate specific media write units of the write data for the write transaction successfully committed to the NVM media.

20. The method of claim 19 , wherein committing the write data to the NVM media comprises:
updating write credits to indicate an available number of writes that can be pending to the NVM media.

21. The method of claim 19 , wherein receiving the write transaction and sending the acknowledgement transaction layer message comprise:
receiving the write transaction over a peripheral component interconnection express (PCIe) link; and
sending the acknowledgement transaction layer message over the PCIe link.

Assignees

• Intel Corp

Inventors

• Tan Kuan Hua
• Khalili Sahar
• Ooi Eng Hun
• Venkatraman Shrinivas
• Patel Dimpesh

Classifications

• G06F9/467 Primary

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F9/546

  Message passing systems or structures, e.g. queues · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title