Write credits management for non-volatile memory

Patent metadata

Field	Value
Publication number	US-2019129656-A1
Application number	US-201816175381-A
Country	US
Kind code	A1
Filing date	Oct 30, 2018
Priority date	Oct 31, 2017
Publication date	May 2, 2019
Grant date	—

Abstract

Systems and methods for synchronizing write credits between a host device and a media controller of a memory system comprising a non-volatile memory (NVM), wherein the host device is configured to maintain a write credit (WC) counter implemented in a memory controller of the host device. The WC counter tracks and limits the number of outstanding write commands which may be issued to the NVM. The host device may query the memory system to obtain status of the available write buffer space in the media controller, and adjust the WC counter based on any detected errors in the write buffer space reported in metadata of read packets sent from the memory system.

First claim

What is claimed is:

1 . A method of accessing a memory system, the method comprising:
setting a write credit counter in a host device to reflect available write buffer space of a write buffer in the memory system; decrementing the write credit counter upon issuing a write command from the host device to the memory system; and incrementing the write credit counter upon receiving at the host device, an indication of additional available write buffer space in the write buffer, from the memory system.

2 . The method of claim 1 , wherein the additional available write buffer space in the write buffer is based on write operations from the write buffer being written to a non-volatile memory in the memory system.

3 . The method of claim 1 , wherein the write command is a persistent memory write (PWRITE) or a write with accompanying parity information (XWRITE).

4 . The method of claim 3 , comprising receiving separate indications for additional available write buffer space for PWRITE and XWRITE in the write buffer, from the memory system.

5 . The method of claim 1 , further comprising receiving an indication of available write buffer space in the write buffer from the memory system in response to a read status command sent to the memory system by the host device.

6 . The method of claim 5 , comprising receiving the indication of the available write buffer space in metadata of one or more read data packets from the memory system.

7 . The method of claim 6 , wherein the indication comprises one of a programmable write credit value, an encoding for write credits, or a mode register bit setting.

8 . The method of claim 6 , further comprising performing an error check, by the host device, on the one or more read data packets.

9 . The method of claim 8 , further comprising, determining, by the host device, an error in the one or more read data packets based on the error check, and issuing another read status command to the memory system.

10 . The method of claim 1 , further comprising preventing write commands being issued by the host device to the memory system if the write credit counter reaches a value of zero.

11 . An apparatus comprising:
a host device comprising a write credit counter, wherein the host device is coupled to a memory system comprising a write buffer, wherein the host device is configured to:
set the write credit counter to reflect available write buffer space of the write buffer;
decrement the write credit counter upon issuing a write command to the memory system; and
increment the write credit counter upon receiving an indication of additional available write buffer space in the write buffer, from the memory system.

12 . The apparatus of claim 11 , wherein the additional available write buffer space in the write buffer is based on write operations from the write buffer written to a non-volatile memory in the memory system.

13 . The apparatus of claim 11 , wherein the write command is a persistent memory write (PWRITE) or a write with accompanying parity information (XWRITE).

14 . The apparatus of claim 13 , wherein the host device is configured to receive separate indications for additional available write buffer space for PWRITE and XWRITE in the write buffer, from the memory system.

15 . The apparatus of claim 11 , wherein the host device is further configured to receive an indication of available write buffer space in the write buffer from the memory system, in response to a read status command sent to the memory system by the host device.

16 . The apparatus of claim 15 , wherein the host device is configured to receive the indication of the available write buffer space in metadata of one or more read data packets from the memory system.

17 . The apparatus of claim 16 , wherein the indication comprises one of a programmable write credit value, an encoding for write credits, or a mode register bit setting.

18 . The apparatus of claim 16 , wherein the host device is further configured to perform an error check on the one or more read data packets.

19 . The apparatus of claim 18 , wherein the host device is further configured to determine an error in the one or more read data packets based on the error check, and issue another read status command to the memory system.

20 . The apparatus of claim 11 , wherein the host device is further configured to prevent write commands from being issued to the memory system if the write credit counter reaches a value of zero.

21 . A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for accessing a memory system, the non-transitory computer-readable storage medium comprising:
code for setting a write credit counter in a host device to reflect available write buffer space of a write buffer in the memory system; code for decrementing the write credit counter upon issuing a write command from the host device to the memory system; and code for incrementing the write credit counter upon receiving at the host device, an indication of additional available write buffer space in the write buffer, from the memory system.

22 . The non-transitory computer-readable storage medium of claim 21 , wherein the additional available write buffer space in the write buffer is based on write operations from the write buffer being written to a non-volatile memory in the memory system.

23 . The non-transitory computer-readable storage medium of claim 21 , wherein the write command is a persistent memory write (PWRITE) or a write with accompanying parity information (XWRITE).

24 . The non-transitory computer-readable storage medium of claim 23 , further comprising code for receiving separate indications for additional available write buffer space for PWRITE and XWRITE in the write buffer, from the memory system.

25 . The non-transitory computer-readable storage medium of claim 21 , further comprising code for receiving an indication of available write buffer space in the write buffer from the memory system in response to a read status command sent to the memory system by the host device.

26 . The non-transitory computer-readable storage medium of claim 25 , further comprising code for receiving the indication of the available write buffer space in metadata of one or more read data packets from the memory system.

27 . The non-transitory computer-readable storage medium of claim 26 , wherein the indication comprises one of a programmable write credit value, an encoding for write credits, or a mode register bit setting.

28 . The non-transitory computer-readable storage medium of claim 26 , further comprising code for performing an error check, by the host device, on the one or more read data packets.

29 . The non-transitory computer-readable storage medium of claim 28 , further comprising, code for determining, by the host device, an error in the one or more read data packets based on the error check, and code for issuing another read status command to the memory system.

30 . An apparatus comprising:
a host device coupled to a memory system, the host device comprising means for tracking write credits, the write credits reflecting available write buffer space of a write buffer in the memory system, wherein the means for tracking write credits comprises

Assignees

• Qualcomm Inc

Inventors

• Bains Kuljit Singh
• Ramanujan Raj
• Queen Wesley
• Wang Liyong

Classifications

• G06F3/0613

  in relation to throughput · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F13/1694

  Configuration of memory controller to different memory types · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title