Semiconductor structure and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-11944017-B2
Application number	US-202318312723-A
Country	US
Kind code	B2
Filing date	May 5, 2023
Priority date	Jul 30, 2018
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
an insulation layer;
a bottom electrode via in the insulation layer, comprising a conductive portion and a capping layer over the conductive portion;
a barrier layer surrounding the bottom electrode via; and
a magnetic tunneling junction (MTJ) over the bottom electrode via.

2. The semiconductor structure of claim 1 , wherein a top surface of the capping layer is coplanar with a top surface of a first portion of the insulation layer.

3. The semiconductor structure of claim 1 , wherein the capping layer comprises an amorphous material.

4. The semiconductor structure of claim 1 , further comprising a bottom electrode, wherein a bottom surface of the bottom electrode is in direct contact with a top surface of the capping layer.

5. The semiconductor structure of claim 1 , wherein a top surface of the bottom electrode via has a first width, a bottom of the MTJ having a second width, the first width being narrower than the second width.

6. The semiconductor structure of claim 1 , wherein a sidewall of the capping layer is in direct contact with the insulation layer.

7. The semiconductor structure of claim 1 , wherein the entire capping layer is within a coverage of a vertical projection area of the MTJ.

8. The semiconductor structure of claim 1 , wherein the barrier layer comprises titanium nitride.

9. A semiconductor memory structure, comprising:
an insulation layer;
a bottom electrode via in the insulation layer;
a barrier layer comprising a first portion surrounding the bottom electrode via and a second portion over the bottom electrode via, wherein the second portion of the barrier layer comprises a concaved recess; and
a magnetic tunneling junction (MTJ) over the bottom electrode via.

10. The semiconductor memory structure of claim 9 , wherein the entire recess is within a coverage of a vertical projection area of the MTJ.

11. The semiconductor memory structure of claim 9 , further comprising a conductive layer disposed in the recess.

12. The semiconductor memory structure of claim 9 , further comprising a bottom electrode between the MTJ and the bottom electrode via, wherein the second portion of the barrier layer is in direct contact with a bottom surface of the bottom electrode.

13. The semiconductor memory structure of claim 9 , wherein the barrier layer comprises tantalum.

14. A semiconductor structure, comprising:
an insulation layer;
a bottom electrode via in the insulation layer;
a bottom electrode over the bottom electrode via;
an magnetic tunneling junction (MTJ) over the bottom electrode; and
a sidewall spacer in direct contact with a sidewall of the MTJ, wherein a bottom portion of the sidewall spacer is at a level below a bottom surface of the bottom electrode.

15. The semiconductor structure of claim 14 , wherein the bottom portion of the sidewall spacer is in direct contact with the insulation layer.

16. The semiconductor structure of claim 14 , wherein a portion of the bottom electrode is free from being vertically overlapping with the bottom electrode via or the sidewall spacer.

17. The semiconductor structure of claim 14 , wherein a first portion of a top surface of the insulation layer is above a bottom surface of the sidewall spacer, and a second portion of the top surface of the insulation layer is below the bottom surface of the sidewall spacer.

18. The semiconductor structure of claim 14 , further comprising a top electrode over the MTJ, wherein a top surface of the top electrode is coplanar with a top surface of the sidewall spacer.

19. The semiconductor structure of claim 14 , further comprising a barrier layer surrounding the bottom electrode via, wherein the sidewall spacer is free from being in direct contact with the barrier layer.

20. The semiconductor structure of claim 14 , wherein the bottom electrode via further comprises an amorphous layer in direct contact with the bottom surface of the bottom electrode.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Tai-Yen
• Chen Yu-Shu
• Huang Chien Chung
• Yang Sin-Yi
• Wang Chen-Jung
• Lin Han-Ting
• Shieh Jyu-Horng
• Fu Qiang

Classifications

• H10N50/85

  Materials of the active region · CPC title

• H10N50/80 Primary

  Constructional details · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title