Display panel

Patent metadata

Field	Value
Publication number	US-11943974-B2
Application number	US-202217674602-A
Country	US
Kind code	B2
Filing date	Feb 17, 2022
Priority date	Jun 19, 2019
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

A display panel includes: a substrate including a first area, a second area, and a third area; a stacked structure corresponding to a plurality of display elements in the second area, the stacked structure including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode; and a plurality of grooves in the third area, wherein the stacked structure includes at least one organic material layer that is disconnected by the plurality of grooves, at least one groove of the plurality of grooves is defined in a first multi-layer including a first lower layer and a first upper layer, and at least one of the first lower layer and the first upper layer includes a plurality of sub-layers.

First claim

What is claimed is:

1. A display panel comprising:
a substrate comprising a first area, a second area, and a third area between the first area and the second area;
a buffer layer on the substrate;
a transistor on the buffer layer, the transistor being located in the second area;
a stack structure in the second area, the stack structure comprising a pixel electrode electrically connected to the transistor, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode;
an encapsulation layer located on the stack structure and comprising at least one inorganic encapsulation layer and an organic encapsulation layer;
at least one partition wall in the third area; and
a plurality of grooves in the third area,
wherein the plurality of grooves comprise a first groove, and a bottom surface of the first groove is located above an upper surface of the buffer layer.

2. The display panel of claim 1 , further comprising an inorganic insulating layer between the buffer layer and the bottom surface of the first groove.

3. The display panel of claim 2 , wherein the inorganic insulating layer comprises a same material as a material of a gate insulating layer between a semiconductor layer and a gate electrode of the transistor.

4. The display panel of claim 1 , further comprising a multilayer film comprising an organic insulating layer on the buffer layer,
wherein the plurality of grooves are formed in the multilayer film,
the organic insulating layer is located in the second area and the third area, and
in the second area, the organic insulating layer is located on a gate electrode of the transistor.

5. The display panel of claim 4 , wherein a metal layer is on the organic insulating layer in the third area, the metal layer comprising a pair of tips protruding toward a center of the first groove.

6. The display panel of claim 5 , wherein the metal layer comprises a stack structure of a titanium layer, an aluminum layer, and a titanium layer.

7. The display panel of claim 4 , further comprising an interlayer insulating layer between the buffer layer and the organic insulating layer and comprising an inorganic insulating material,
wherein the interlayer insulating layer has a hole corresponding to the first groove.

8. The display panel of claim 1 , wherein a portion of the organic encapsulation layer is located in the first groove.

9. The display panel of claim 1 , further comprising a planarization layer on the encapsulation layer to overlap a portion of the encapsulation layer in the third area.

10. The display panel of claim 1 , wherein the at least one partition wall comprises two partition walls in the third area, and
at least one of the plurality of grooves is located between the two partition walls.

11. An electronic apparatus comprising:
a display panel comprising a first area, a second area, and a third area between the first area and the second area; and
a component located below the display panel and corresponding to the first area,
wherein the display panel comprises:
a substrate;
a buffer layer on the substrate;
a transistor on the buffer layer, the transistor being located in the second area;
a stack structure in the second area, the stack structure comprising a pixel electrode electrically connected to the transistor, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode;
an encapsulation layer located on the stack structure and comprising at least one inorganic encapsulation layer and an organic encapsulation layer;
at least one partition wall in the third area; and
a plurality of grooves in the third area, and
wherein the plurality of grooves comprise a first groove, and a bottom surface of the first groove is located above an upper surface of the buffer layer.

12. The electronic apparatus of claim 11 , wherein the component comprises a camera or a sensor.

13. The electronic apparatus of claim 11 , wherein the display panel further comprises an inorganic insulating layer between the buffer layer and the bottom surface of the first groove.

14. The electronic apparatus of claim 13 , wherein the inorganic insulating layer comprises a same material as a material of a gate insulating layer between a semiconductor layer and a gate electrode of the transistor.

15. The electronic apparatus of claim 11 , wherein the display panel further comprises a multilayer film comprising an organic insulating layer on the buffer layer, and
the plurality of grooves are formed in the multilayer film,
the organic insulating layer is located in the second area and the third area, and
in the second area, the organic insulating layer is located on a gate electrode of the transistor.

16. The electronic apparatus of claim 15 , wherein a metal layer is on the organic insulating layer in the third area, the metal layer comprising a pair of tips protruding toward a center of the first groove.

17. The electronic apparatus of claim 16 , wherein the metal layer comprises a stack structure of a titanium layer, an aluminum layer, and a titanium layer.

18. The electronic apparatus of claim 15 , wherein the display panel further comprises an interlayer insulating layer between the buffer layer and the organic insulating layer and comprising an inorganic insulating material, and
the interlayer insulating layer has a hole corresponding to the first groove.

19. The electronic apparatus of claim 11 , wherein a portion of the organic encapsulation layer is located in the first groove.

20. The electronic apparatus of claim 11 , wherein the display panel further comprises a planarization layer on the encapsulation layer to overlap a portion of the encapsulation layer in the third area.

21. The electronic apparatus of claim 11 , wherein the at least one partition wall comprises two partition walls in the third area, and
at least one of the plurality of grooves is located between the two partition walls.

Assignees

• Samsung Display Co Ltd

Inventors

• Seon Jongbaek
• Lee Jaehak
• Shin Juncheol
• Chae Kyungchan
• Choi Jieun

Classifications

• H10K59/87 Primary

  Passivation; Containers; Encapsulations · CPC title

• H10K59/8731

  multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers · CPC title

• H10K59/124 Primary

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K59/122 Primary

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10K59/60

  OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes · CPC title