Single-ended direct interface DAC feedback and current sink photo-diode sensor

Patent metadata

Field	Value
Publication number	US-11942967-B2
Application number	US-202318093021-A
Country	US
Kind code	B2
Filing date	Jan 4, 2023
Priority date	Nov 8, 2019
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

An analog to digital converter (ADC) that is configured to service a photo-diode includes a capacitor and a self-referenced latched comparator. The capacitor produces a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The self-referenced latched comparator generates a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. Also, one or more processing modules executes operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. An N-bit DAC generates the DAC source current based on the second digital signal, and an M-bit DAC generates the DAC sink current based on the third digital signal. The DAC source current and/or the DAC sink current tracks the photo-diode current.

First claim

What is claimed is:

1. An analog to digital converter (ADC) comprising:
a capacitor that is operably coupled to a photo-diode and configured to produce a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current;
a self-referenced latched comparator operably coupled to the photo-diode and the capacitor and configured to generate a first digital signal that is based on the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator;
an N-bit accumulator that is operably coupled to self-referenced latched comparator and configured to process the first digital signal to generate a second digital signal, wherein N is a positive integer;
an N-bit DAC that is operably coupled to the N-bit accumulator and configured to generate the DAC source current based on the second digital signal; and
a current sink that is operably coupled to the self-referenced latched comparator and configured to provide a path to sink current when the photo-diode current has a value of zero.

2. The ADC of claim 1 , wherein the current sink is further configured to configured to generate a sink current based on the second digital signal, wherein the at least one of the DAC source current or the sink current tracks the photo-diode current.

3. The ADC of claim 1 , wherein the ADC is coupled to the photo-diode via a single line.

4. The ADC of claim 1 , wherein the first digital signal is based on a difference between the photo-diode voltage and the threshold voltage associated with the self-referenced latched comparator.

5. The ADC of claim 1 further comprising:
a decimation filter operably coupled to the N-bit accumulator and configured to process the second digital signal to generate a third digital signal having a lower sampling rate and a higher resolution than the second digital signal.

6. The ADC of claim 1 , wherein the current sink is operably coupled to the self-referenced latched comparator via a switch that is controlled based on the second digital signal.

7. The ADC of claim 6 , wherein the current sink is further configured to maintain a voltage at an input of the self-referenced latched comparator to be same as the threshold voltage associated with the self-referenced latched comparator when the photo-diode current has a value of zero.

8. The ADC of claim 1 , wherein the self-referenced latched comparator further comprising:
a first inverter operably coupled to the photo-diode and the capacitor and configured to compare the photo-diode voltage to the threshold voltage associated with the self-referenced latched comparator that corresponds to a threshold voltage of the first inverter;
a second inverter operably coupled to the first inverter; and
a digital circuit operably coupled to the second inverter and configured to output the first digital signal.

9. The ADC of claim 1 , wherein the self-referenced latched comparator further comprising:
a first inverter operably coupled to the photo-diode and the capacitor and configured to compare the photo-diode voltage to the threshold voltage associated with the self-referenced latched comparator that corresponds to a threshold voltage of the first inverter;
a second inverter operably coupled to the first inverter;
a third inverter including an input operably coupled to an output of the second inverter and an output operably coupled to a node coupling an output of the first inverter to an input of the second inverter via a switch to facilitate operation of the self-referenced latched comparator in accordance with a sampling mode and a latched mode; and
a digital circuit operably coupled to the second inverter and configured to output the first digital signal.

10. The ADC of claim 1 , wherein:
the photo-diode is implemented off chip; and
the capacitor, the self-referenced latched comparator, the N-bit accumulator, the N-bit DAC, and the current sink are implemented on chip.

11. The ADC of claim 1 , wherein the self-referenced latched comparator operably coupled to the photo-diode and the capacitor is further configured to:
compare the photo-diode voltage to the threshold voltage;
generate a first digital value within the first digital signal based on the photo-diode voltage comparing favorably to the threshold voltage; and
generate a second digital value within the first digital signal based on the photo-diode voltage comparing unfavorably to the threshold voltage.

12. The ADC of claim 1 , wherein the ADC and the photo-diode are implemented within a photo-diode image sensor.

13. The ADC of claim 1 , wherein:
the ADC and the photo-diode are implemented within a photo-diode image sensor in a device stack-up;
a printed circuit board (PCB) is implemented in a first portion of the device stack-up;
the ADC is implemented in a second portion of the device stack-up that is next to the first portion of the device stack-up; and
the photo-diode is implemented in a third portion of the device stack-up that is next to the second portion of the device stack-up.

14. An analog to digital converter (ADC) comprising:
a capacitor that is operably coupled to a photo-diode and configured to produce a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current;
a self-referenced latched comparator operably coupled to the photo-diode and the capacitor and configured to generate a first digital signal that is based on the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator;
an N-bit accumulator that is operably coupled to self-referenced latched comparator and configured to process the first digital signal to generate a second digital signal, wherein N is a positive integer;
an N-bit DAC that is operably coupled to the N-bit accumulator and configured to generate the DAC source current based on the second digital signal;
a current sink that is operably coupled to the self-referenced latched comparator and configured to provide a path to sink current when the photo-diode current has a value of zero, wherein the current sink is operably coupled to the self-referenced latched comparator via a switch that is controlled based on the second digital signal; and
a decimation filter operably coupled to the N-bit accumulator and configured to process the second digital signal to generate a third digital signal having a lower sampling rate and a higher resolution than the second digital signal.

15. The ADC of claim 14 , wherein the current sink is further configured to configured to generate a sink current based on the second digital signal, wherein the at least one of the DAC source current or the sink current tracks the photo-diode current.

16. The ADC of claim 14 , wherein the ADC is coupled to the photo-diode via a single line.

17. The ADC of claim 14 , wherein the first digital signal is based on a difference between the photo-diode voltage and the threshold voltage associated with the self-referenced latched comparator.

18. The ADC of claim 14 , wherein the current sink is further configured to maintain a voltage at an input of the self-referenced latched comparator to be same as the threshold voltage associated with the self-referenced latched comparator when the photo-diode current has a value of zero.

19. The ADC of claim 14 , wherein the ADC and the photo-diode are implemented within a photo-diode image sensor.

20. The ADC o

Assignees

• Sigmasense Llc

Inventors

• Huynh Phuong

Classifications

• H10F39/803

  Pixels having integrated switching, control, storage or amplification elements · CPC title

• H03M3/462 Primary

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M1/0626

  by filtering · CPC title

• H03M3/32

  with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed · CPC title

• H03M3/476

  Non-linear conversion systems · CPC title