Pulse-generator-based bias-level sensors for reciprocal quantum logic

Patent metadata

Field	Value
Publication number	US-11942937-B2
Application number	US-202217736517-A
Country	US
Kind code	B2
Filing date	May 4, 2022
Priority date	May 4, 2022
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

Pulse-generator-based reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors include pulse generators having strengthened or weakened bias taps (transformer couplings to RQL AC clock resonators or DC bias lines) as compared to bias taps of Josephson transmission lines in the operational RQL circuitry, or Josephson junctions (JJs) with larger or smaller critical currents as compared to JJs in the operational RQL circuitry. Pulse generators with weakened bias taps or larger JJs can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. The bias-level sensors can be staged by relative strength to indicate whether a provided bias value is an improvement when varied over a range.

First claim

What is claimed is:

1. A reciprocal quantum logic (RQL) system comprising:
an RQL integrated circuit (IC) comprising:
operational RQL circuitry configured to perform one or more computational functions, the operational RQL circuitry comprising a first Josephson junction (JJ), the operational RQL circuitry being inductively coupled to a bias signal source to provide biasing to the first JJ; and
bias-level sensing circuitry configured to sense one or more parameters of bias signals provided to the operational RQL circuitry, the bias-level sensing circuitry comprising at least first and second bias-level sensors, each of the first and second bias-level sensors comprising a respective pulse generator comprising a second JJ coupled to the bias signal source, the pulse generator having an output configured to provide a reciprocal pair of single flux quantum (SFQ) pulses with each AC cycle of an AC signal provided by the bias signal source based on the amplitude of the AC signal being within operating margins of the pulse generator.

2. The system of claim 1 , wherein the second JJ is sized to have a larger critical current than the first JJ.

3. The system of claim 1 , wherein the pulse generator of the second bias-level sensor is more weakly coupled to the bias signal source than the pulse generator of the first bias-level sensor, and a lower AC bias amplitude limit of an operating range of the second bias-level sensor is at about a centroid of an operating range of the operational RQL circuitry.

4. The system of claim 1 , wherein the bias-level sensing circuitry comprises an RQL scan register comprising:
an input line comprising a first plurality of JTLs;
an output line comprising a second plurality of JTLs;
a plurality of RQL gates each having a respective first input, a respective second input coupled to the input line, and a respective output coupled to the output line; and
a plurality of bias-level sensors including the at least first and second bias-level sensors, each of the plurality of bias-level sensors having a respective output coupled to the first input of a corresponding one of the plurality of RQL gates.

5. The system of claim 4 , wherein each of the bias-level sensors in the bias-level sensing circuitry is transformer-coupled to an AC clock resonator or DC bias line of the RQL integrated circuit at a respective different location along the AC clock resonator or DC bias line.

6. The system of claim 4 , wherein the first bias-level sensor is configured to have different AC or DC operating margins from the second bias-level sensors, and a third bias-level sensor of the plurality of bias-level sensors is configured to have different AC or DC operating margins from both of the first bias-level sensor and the second bias-level sensor.

7. The system of claim 6 , wherein a bias tap inductor of the pulse generator of the second bias-level sensor is larger than a bias tap inductor of the pulse generator of the first bias-level sensor, and a bias tap inductor of a pulse generator of the third bias-level sensor is larger than the bias tap inductor of the pulse generator of the second bias-level sensor.

8. The system of claim 6 , wherein the respective second JJ of the pulse generator of the second bias-level sensor has a larger critical current than the respective second JJ of the pulse generator of the first bias-level sensor, and a respective second JJ of a pulse generator of the third bias-level sensor has a larger critical current than the respective second JJ of the pulse generator of the second bias-level sensor.

9. The system of claim 4 , wherein a sample signal assertion provided to the input line results as a number of output assertions serially provided from the output line, the number of output assertions being based on a number of the plurality of bias-level sensors that are respectively biased by the bias signal source within their respective operating ranges.

10. The system of claim 4 , wherein:
the pulse generator of the first bias-level sensor is coupled to first and second AC clock resonators of the RQL system to provide the respective AC signal provided to the first pulse generator as a 45° phase AC clock, and
the pulse generator of the second bias-level sensor is coupled to first and second AC clock resonators of the RQL system to provide the respective AC signal provided to the second pulse generator as a 135° phase AC clock.

11. The system of claim 4 , wherein:
the pulse generator of the first bias-level sensor is coupled to first and second AC clock resonators of the RQL system to provide the respective AC signal provided to the first pulse generator as a 225° phase AC clock, and
the pulse generator of the second bias-level sensor is coupled to first and second AC clock resonators of the RQL system to provide the respective AC signal provided to the second pulse generator as a 315° phase AC clock.

12. A system comprising a first instance of the bias-level sensing circuitry of claim 4 and a second instance of the bias-level sensing circuitry of claim 4 , wherein:
respective pulse generators of each of the respective plurality of bias-level sensors of the first instance of the bias-level sensing circuitry are coupled to first and second AC clock resonators of the RQL system to provide the respective AC signal of the first instance of the bias-level sensing circuitry as a 45° phase AC clock;
respective pulse generators of each of the respective plurality of bias-level sensors of the second instance of the bias-level sensing circuitry are coupled to first and second AC clock resonators of the RQL system to provide the respective AC signal of the first instance of the bias-level sensing circuitry as a 135° phase AC clock.

13. A system comprising a first instance of the bias-level sensing circuitry of claim 4 and a second instance of the bias-level sensing circuitry of claim 4 , wherein:
respective pulse generators of each of the respective plurality of bias-level sensors of the first instance of the bias-level sensing circuitry are coupled to first and second AC clock resonators of the RQL system to provide the respective AC signal of the first instance of the bias-level sensing circuitry as a 225° phase AC clock;
respective pulse generators of each of the respective plurality of bias-level sensors of the second instance of the bias-level sensing circuitry are coupled to first and second AC clock resonators of the RQL system to provide the respective AC signal of the first instance of the bias-level sensing circuitry as a 315° phase AC clock.

14. A method of calibrating bias signals provided to operational reciprocal quantum logic (RQL) circuitry in an RQL integrated circuit (IC), the method comprising:
inputting a sample signal to RQL AC bias sampler wrapper circuitry comprising a plurality of RQL AC bias samplers, more than one of the plurality of AC bias samplers comprising:
a pulse generator driven by an AC bias signal derived from one or more AC clock resonators, the pulse generator having at least one of:
a weakened AC clock resonator bias tap to the one or more AC clock resonators of the RQL IC as compared to an AC clock resonator bias tap of a JTL in the operational RQL circuitry, or
a Josephson junction (JJ) having a larger critical current than a JJ in the operational RQL circuitry; and

an RQL gate having a first input coupled to an output of the pulse generator and a second input coupled to a sample signal input line comprising a JTL;

observing an output of the AC bias sampler wrapper circuitry;
varying an amplitude of an AC clock signal provided to the operational RQL circuitry via the A

Assignees

• Wallace Charles Ryan
• Nielsen Max E
• Braun Alexander Louis
• Dosch Daniel George
• Pleim Kurt
• Dai Haitao O
• Northrop Grumman Systems Corp

Inventors

• Wallace Charles Ryan
• Nielsen Max E
• Braun Alexander Louis
• Dosch Daniel George
• Pleim Kurt
• Dai Haitao O

Classifications

• H03K19/195 Primary

  using superconductive devices · CPC title

• H03K3/38

  by the use, as active elements, of superconductive devices · CPC title

• H03K19/1774 Primary

  for global signals, e.g. clock, reset · CPC title

• H03K19/17744

  for input/output signals · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title