Transconductance amplifier for buck-boost converter

Patent metadata

Field	Value
Publication number	US-11942866-B2
Application number	US-202117381679-A
Country	US
Kind code	B2
Filing date	Jul 21, 2021
Priority date	Sep 3, 2020
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

An error amplifier includes an output pin coupled to a pulse width modulation (PWM) comparator of a buck-boost converter. A first transconductance amplifier adjusts an output current at the output pin and operates in a constant voltage mode. The first transconductance amplifier includes a first positive input to receive a first voltage reference and a first negative input coupled to a tap point of a voltage divider coupled between a voltage bus and a ground of the buck-boost converter. A second transconductance amplifier also adjusts the output current at the output pin and operates in a constant current mode. The second transconductance amplifier includes a second positive input to receive a second voltage reference and a second negative input coupled to a current sense amplifier, the current sense amplifier being coupled to a sense resistor positioned inline along the voltage bus.

First claim

What is claimed is:

1. An error amplifier comprising:
an output pin coupled to a pulse width modulation (PWM) comparator of a buck-boost converter;
a first transconductance amplifier to adjust an output current at the output pin, wherein the first transconductance amplifier operates in a constant voltage mode and comprises:
a first positive input to receive a first voltage reference; and
a first negative input coupled to a tap point of a voltage divider coupled between a voltage bus and a ground of the buck-boost converter;

a second transconductance amplifier to also adjust the output current at the output pin, wherein the second transconductance amplifier operates in a constant current mode and comprises:
a second positive input to receive a second voltage reference; and
a second negative input coupled to a current sense amplifier, the current sense amplifier being coupled to a sense resistor positioned inline along the voltage bus.

2. The error amplifier of claim 1 , further comprising a temperature compensation circuit to maintain accuracy of the output current by tracking transconductance variation according to temperature-to-load-current variation, the temperature compensation circuit comprising:
a bandgap-to-current circuit to convert a bandgap voltage reference of the buck-boost converter to a bandgap-dependent current; and
a beta multiplier coupled to the bandgap-to-current circuit, the beta multiplier to:
generate a load bias current, which is based on the bandgap-dependent current, to bias a current source that is coupled to the output pin; and
generate a temperature-dependent bias current to bias current output by at least one of the first transconductance amplifier or the second transconductance amplifier.

3. The error amplifier of claim 2 , wherein the bandgap-to-current circuit comprises:
a metal-oxide-semiconductor field-effect transistor (MO SFET) with a source coupled to a supply voltage;
a voltage divider having a variable resistor and that is coupled between a drain of the MOSFET and the ground; and
a comparator to drive a gate of the MOSFET based on inputs comprising the bandgap voltage and a middle tap point of the voltage divider.

4. The error amplifier of claim 1 , further comprising an offset cancellation circuitry coupled to outputs of the first transconductance amplifier and the second transconductance amplifier, the offset cancellation circuitry to:
one of detect a first direct current (DC) voltage offset at an input of the first transconductance amplifier while in the constant voltage mode or a second DC voltage offset at an input of the second transconductance amplifier while in the constant current mode;
in response to detection of the first DC offset, sink a first equivalent current from the first transconductance amplifier to cancel the first DC voltage offset, wherein the first equivalent current corresponds to a programmable transconductance of the first transconductance amplifier; and
in response to detection of the second DC offset, sink a second equivalent current from the second transconductance amplifier to cancel the second DC voltage offset, wherein the second equivalent current corresponds to a programmable transconductance of the second transconductance amplifier.

5. The error amplifier of claim 1 , further comprising:
a current source coupled between a supply voltage and the output pin;
a first diode coupled between output pin and a first output of the first transconductance amplifier;
a second diode coupled between the output pin and a second output of the second transconductance amplifier; and
a minimum current generator having current inputs from the first output and the second output and an output connected to the output pin, the minimum current generator to:
determine a minimum current between the first output and the second output; and
supply the minimum current to the output pin.

6. The error amplifier of claim 1 , further comprising a programmable transconductance circuit coupled to an output of at least one of the first transconductance amplifier or the second transconductance amplifier, wherein the programmable transconductance circuit comprises a bank of MOSFETs in which a gate of at least some of the MOSFETs are coupled to control logic to be trimmed in order to adjust an output current supplied to the output pin.

7. The error amplifier of claim 1 , further comprising:
a first boost transconductance amplifier to receive, as inputs, the first positive input and the first negative input of the first transconductance amplifier, and to supply an adjustment in output current to the first transconductance amplifier proportional to a first difference between the first positive input and the first negative input; and
a second boost transconductance amplifier to receive, as inputs, the second positive input and the second negative input of the first transconductance amplifier, and to supply an adjustment in output current to the second transconductance amplifier proportional to a second difference between the second positive input and the second negative input.

8. The error amplifier of claim 7 , wherein a threshold minimum voltage source is supplied on each of the first and second positive inputs of the first boost transconductance amplifier and the second boost transconductance amplifier, respectively, to provide a minimum starting point for boosting.

9. The error amplifier of claim 7 , further comprising a dynamic source current generator coupled to each of the first boost transconductance amplifier and the second boost transconductance amplifier, the dynamic source current generator to:
detect saturation of one of the first transconductance amplifier or the second transconductance amplifier; and
provide a source current to the output pin in response to the saturation of the one of the first transconductance amplifier or the second transconductance amplifier, the source current being proportional to an input difference of respective positive and negative inputs of the one of the first transconductance amplifier or the second transconductance amplifier that saturates.

10. An integrated circuit (IC) controller for a Universal Serial Bus (USB) Type-C device, the IC controller comprising:
a buck-boost converter to switch an output voltage of a voltage bus of the USB Type-C device that can swing up to at least 24 volts; and
an error amplifier coupled between an output and an input of the buck-boost converter, wherein the error amplifier comprises:
an output pin coupled to a pulse width modulation (PWM) comparator of the buck-boost converter;
a first transconductance amplifier to adjust an output current at the output pin, wherein the first transconductance amplifier operates in a constant voltage mode and comprises:
a first positive input to receive a first voltage reference; and
a first negative input coupled to a tap point of a voltage divider coupled between a voltage bus and a ground of the buck-boost converter;

a second transconductance amplifier to also adjust the output current at the output pin, wherein the second transconductance amplifier operates in a constant current mode and comprises:
a second positive input to receive a second voltage reference; and
a second negative input coupled to a current sense amplifier, the current sense amplifier being coupled to a sense resistor positioned inline along the voltage bus.

11. The IC controller of claim 10 , wherein the error amplifier further comprises a temperature compensation circuit to maintain accuracy of the output current by tracking transconductance variation according to temperature-to-load-current variation, the temperature compensation

Assignees

• Cypress Semiconductor Corp

Inventors

• Karri Rajesh
• Khamesra Arun

Classifications

• H02M3/1582 Primary

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H03F1/0227

  using supply converters · CPC title

• H03F1/301

  in MOSFET amplifiers (H03F1/303, H03F1/305, H03F1/308 take precedence) · CPC title

• H03F2200/351

  Pulse width modulation being used in an amplifying circuit · CPC title