Electrostatic discharge protection cell and antenna integrated with through silicon via

US11942441B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11942441-B2
Application numberUS-202117480329-A
CountryUS
Kind codeB2
Filing dateSep 21, 2021
Priority dateAug 30, 2021
Publication dateMar 26, 2024
Grant dateMar 26, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a through-silicon via (TSV) in a TSV zone in a substrate and the TSV extends through the substrate; an ESD cell proximal to a first end of the TSV and in contact with the TSV zone, the ESD cell including a set of diodes electrically connected in parallel to each other; an antenna pad electrically connected to a second end of the TSV; and an antenna electrically connected to the antenna pad and extending in a first direction, the first direction is parallel to a major axis of the TSV. The semiconductor device includes a conductive pillar extending parallel to the TSV at a same side of the substrate as the antenna pad, wherein a first end of the conductive pillar electrically connects to the antenna pad, and a second end of the conductive pillar electrically connects to the set of diodes of the ESD cell.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising; a through-silicon via (TSV) in a TSV zone in a substrate, wherein the TSV extends through the substrate; an ESD cell proximal to a first end of the TSV and in contact with the TSV zone, the ESD cell comprising a set of diodes electrically connected in parallel to each other; an antenna pad electrically connected to a second end of the TSV; an antenna electrically connected to the antenna pad and extending in a first direction, wherein the first direction is parallel to a major axis of the TSV; and a conductive pillar extending parallel to the TSV at a same side of the substrate as the antenna pad in the first direction, wherein a first end of the conductive pillar electrically connects to the antenna pad, and a second end of the conductive pillar electrically connects to the set of diodes of the ESD cell. 2. The semiconductor device of claim 1 , wherein the antenna pad is in direct contact with the second end of the TSV. 3. The semiconductor device of claim 1 , wherein the antenna is a first separation distance from the TSV, the conductive pillar is a second separation distance from the TSV, and the second separation distance is larger than the first separation distance. 4. The semiconductor device of claim 3 , further comprising a set of antenna lines extending parallel to the TSV at the first separation distance from the TSV and distributed through around a circumference of the TSV, wherein the first separation distance is a smaller distance than a smallest distance between the TSV and a perimeter of the TSV zone. 5. The semiconductor device of claim 1 , further comprising a set of ESD cells proximal to the first end of the TSV, wherein the set of ESD cells is arranged along a perimeter of the TSV zone and extends around the TSV zone. 6. The semiconductor device of claim 1 , wherein a number of diodes in each ESD cell is not less than 2 and not more than 20. 7. The semiconductor device of claim 1 , wherein the conductive pillar comprises a set of vias and line segments. 8. The semiconductor device of claim 1 , wherein the antenna comprises a conductive material having a smooth sidewall. 9. A semiconductor device, comprising: a through-silicon via (TSV) extending through a substrate and a TSV zone of a semiconductor device interconnect structure; a set of ESD cells in proximity to a first side of the substrate, wherein the set of ESD cells extend around a circumference of the TSV, and wherein each ESD cell of the set of ESD cells comprises a set of diodes electrically connected in parallel, and wherein a first end of the TSV is at a different side of the substrate from the set of ESD cells, and a second end of the TSV is at the same side of the substrate from the set of ESD cells; a set of conductive pillars, wherein a first end of each conductive pillar electrically connects to one ESD cell, and a second end of each conductive pillar is proximal to the second end of the TSV; an antenna pad, wherein the antenna pad is proximal to the second end of the TSV, electrically connects to the second end of the TSV, and electrically connects to conductive pillars of the set of conductive pillars; and a set of antennas extending through the TSV zone parallel to the TSV and electrically connected to the antenna pad. 10. The semiconductor device of claim 9 , wherein each ESD cell of the set of ESD cells has a same number of diodes. 11. The semiconductor device of claim 10 , wherein a number of diodes in each ESD cell of the set of ESD cells ranges from not less than 2 to not more than 20. 12. The semiconductor device of claim 9 , wherein each antenna of the set of antennas further comprises an antenna high aspect ratio contact (antenna HARC). 13. The semiconductor device of claim 9 , wherein each conductive pillar of the set of conductive pillars further comprises an ESD high aspect ratio contact (ESD HARC). 14. The semiconductor device of claim 9 , wherein each conductive pillar of the set of conductive pillars further comprises a plurality of contacts and conductive lines electrically connecting a corresponding ESD cell of the set of ESD cells to the antenna pad. 15. The semiconductor device of claim 9 , wherein the antenna pad is in direct contact with the second end of the TSV. 16. A semiconductor device, comprising; a through-silicon via (TSV) in a substrate, wherein the TSV extends through the substrate; an ESD cell in the substrate, the ESD cell comprising a set of diodes electrically connected in parallel to each other; an antenna pad electrically connected to the TSV; an antenna electrically connected to the antenna pad and extending in a first direction, wherein the first direction is parallel to a major axis of the TSV; and a conductive pillar electrically connecting the antenna pad to the set of diodes of the ESD cell, wherein the antenna is between the TSV and the conductive pillar. 17. The semiconductor device of claim 16 , further comprising a second TSV in the substrate, wherein the second TSV is between the TSV and the antenna. 18. The semiconductor device of claim 16 , further comprising a semiconductor material surrounding the TSV, wherein the antenna extends through the semiconductor material. 19. The semiconductor device of claim 16 , wherein the antenna pad directly contacts the TSV. 20. The semiconductor device of claim 16 , further comprising: a dielectric layer between the antenna pad and the TSV; and a contact extending through the dielectric layer, wherein the contact electrically connects the TSV to the antenna pad.

Assignees

Inventors

Classifications

  • TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

  • by forming conductive members before forming protective insulating material · CPC title

  • the interconnections being through-semiconductor vias · CPC title

  • Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

  • of isolation region based on field-effect · CPC title

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What does patent US11942441B2 cover?
A semiconductor device includes a through-silicon via (TSV) in a TSV zone in a substrate and the TSV extends through the substrate; an ESD cell proximal to a first end of the TSV and in contact with the TSV zone, the ESD cell including a set of diodes electrically connected in parallel to each other; an antenna pad electrically connected to a second end of the TSV; and an antenna electrically c…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd, Tsmc China Company Ltd
What technology area does this patent fall under?
Primary CPC classification H10W42/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 26 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).