Apparatuses and systems having ball grid arrays and associated microelectronic devices and device packages

Patent metadata

Field	Value
Publication number	US-11942404-B2
Application number	US-202117411879-A
Country	US
Kind code	B2
Filing date	Aug 25, 2021
Priority date	Aug 25, 2020
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

First claim

What is claimed is:

1. An apparatus, comprising:
a device substrate comprising a semiconductor material and bond pads coupled with an active surface of the device substrate;
a package substrate secured to the device substrate, the package substrate configured to route signals to and from the bond pads; and
a ball grid array supported on, and electrically connected to, the package substrate, the ball grid array comprising an odd number of columns, such that the ball grid array comprises a central column having equal numbers of other columns on opposite sides of the central column;
wherein each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal is located in the central column of the ball grid, array,
wherein a total number of balls in the ball grid array is between about 115 and about 120.

2. The apparatus of claim 1 , wherein each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal is laterally and longitudinally spaced from a nearest ball of the ball grid array positioned and configured to carry a data signal by at least one column of the ball grid array.

3. The apparatus of claim 1 , wherein each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal is spaced from a perimeter of the ball grid array by at least one row.

4. The apparatus of claim 1 , wherein the device substrate is secured to the package substrate by a direct chip attach.

5. The apparatus of claim 1 , wherein the ball grid array is at least substantially reflectively symmetrical across the central column.

6. The apparatus of claim 1 , wherein each ball of the ball grid array positioned and configured to carry a data signal is located only diagonally adjacent to any other directly adjacent balls of the ball grid array positioned and configured to carry a data signal.

7. The apparatus of claim 1 , wherein a perimeter of the ball grid array is at least substantially free of balls positioned and configured to carry data signals.

8. The apparatus of claim 1 , wherein each ball of the ball grid array located laterally and longitudinally adjacent to each ball of the ball grid array positioned and configured to carry a data signal is configured to carry a voltage, connect to ground, or connect to a calibration circuit.

9. An apparatus, comprising:
a device substrate comprising semiconductor material and bond pads coupled with an active surface of the device substrate,
a package substrate secured to the device substrate, the package substrate configured to route signals to and from the bond pads, and
a ball grid array supported on, and electrically connected to, the package substrate, the ball grid array comprising an odd number of columns, such that the ball grid array comprises a central column having equal numbers of other columns on opposite sides of the central column,
wherein each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal is located in the central column of the ball grid array,
wherein a number of the balls of the ball grid array positioned and configured to carry a data signal is between about one-eighth and about one-fourth a number of the balls of the ball grid array positioned and configured to carry a voltage or connect to ground;
wherein a number of the balls of the ball grid array positioned and configured to carry a data signal is between about two-fifths about nine-tenths a number of the balls of the ball grid array positioned and configured to connect to input/output memory supply voltage.

10. The apparatus of claim 9 , wherein a number of the balls of the ball grid array positioned and configured to carry a data signal is between about one-fourth and about one-half a number of the balls of the ball grid array positioned and configured to connect to core system voltage or to core system ground.

11. The apparatus of claim 9 , wherein a total number of the balls of the ball grid array is between about 115 and about 120.

12. The apparatus of claim 9 , wherein a number of the balls of the ball grid array positioned and configured to carry a data signal is about equal to a number of the balls of the ball grid array positioned and configured to connect to output driver voltage.

13. The apparatus of claim 9 , wherein a number of the balls of the ball grid array positioned and configured to carry a data signal is about four times a number of the balls of the ball grid array positioned and configured to connect to word line voltage.

14. The apparatus of claim 1 , wherein a number of the balls of the ball grid array positioned and configured to carry a data signal is between about one-eighth and about one-fourth a number of the balls of the ball grid array positioned and configured to carry a voltage or connect to ground and wherein a number of the balls of the ball grid array positioned and configured to carry a data signal is about four times a number of the balls of the ball grid array positioned and configured to connect to word line voltage.

15. An apparatus, comprising:
a first memory device, comprising:
a device substrate comprising a semiconductor material and bond pads coupled with an active surface of the device substrate;
a package substrate secured to the device substrate, the package substrate configured to route signals to and from the bond pads; and
a ball grid array supported on, and electrically connected to, the package substrate, the ball grid array comprising an odd number of columns, such that the ball grid array comprises a central column having equal numbers of other columns on opposite sides of the central column;

a second memory device; and
a printed circuit board interposed between, and secured to, each of the first memory device and the second memory device;
wherein each ball of the ball grid array of the first memory device positioned and configured to carry a clock signal or a strobe signal is located in the central column of the ball grid array;
wherein a total number of balls in the ball grid array is between about 115 and about 120.

16. The apparatus of claim 15 , wherein the second memory device comprises a second ball grid array, the second ball grid array being rotationally mirrored across the printed circuit board relative to the ball grid array of the first memory device.

17. The apparatus of claim 16 , wherein the printed circuit board comprises an electrical conductor located within the printed circuit board, the electrical conductor electrically connected to a first ball of the ball grid array of the first memory device positioned and configured to carry a clock signal or a strobe signal, the electrical conductor electrically connected to a second ball of the ball grid array of the second memory device positioned and configured to carry a clock signal or a strobe signal, the electrical conductor extending at least substantially perpendicular to a major surface of the printed circuit board over at least substantially an entire distance between the first ball and the second ball.

18. The apparatus of claim 16 , wherein the device substrate of the first memory device is secured to the package substrate by a direct chip attach.

19. The apparatus of claim 18 , wherein the first memory device is configured as a single die package, comprises a stack of device substrates interconnected to one another by through-silicon vias, or comprises a stack of device substrates interconnected to one another by wire bonds.

20. A system,

Assignees

• Micron Technology Inc

Inventors

• Leslie Matthew B
• Hollis Timothy M
• Cyr Scott R
• Moxham Stephen F
• Prather Matthew A
• Smith Scott

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title