Built-in self-test for die-to-die physical interfaces

Patent metadata

Field	Value
Publication number	US-11940491-B2
Application number	US-202318303401-A
Country	US
Kind code	B2
Filing date	Apr 19, 2023
Priority date	May 13, 2021
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

First claim

What is claimed is:

1. An apparatus, comprising:
a particular integrated circuit, included in a particular chip package, including:
a particular interface circuit that includes a first set transmit pins and a first set of receive pins;
a particular set of switch circuits configured to couple, when enabled, one or more of the first set of receive pins to a corresponding one or more of the first set of transmit pins; and
a particular test circuit configured to enable, based on a particular mapping that is associated with a first test mode, a first subset of switch circuits of the particular set of switch circuits, coupling a first subset of the first set of receive pins to a first subset of the first set of transmit pins;
wherein the first subset of switch circuits is further configured to route a test packet, received via the first subset of receive pins, to the first subset of transmit pins, the routing bypassing the particular test circuit; and
wherein the particular test circuit is further configured to enable, based on a different mapping determined based on a second test mode, a second subset of switch circuits of the particular set of switch circuits, coupling a second subset of the first set of receive pins to a second subset of the first set of transmit pins.

2. The apparatus of claim 1 , further comprising:
a different integrated circuit, included in the particular chip package, including:
a different interface circuit that includes a second set transmit pins coupled to the first set of receive pins and a second set of receive pins coupled to the first set of transmit pins; and
a different test circuit configured to send via a third subset of the second set of transmit pins, the test packet, wherein the third subset of the second set of transmit pins is coupled to the first subset of the first set of receive pins.

3. The apparatus of claim 2 , wherein the different test circuit is further configured to send, via the second set of transmit pins to the particular test circuit, an indication of a currently selected test mode.

4. The apparatus of claim 2 , wherein the different test circuit is further configured to receive, via a third subset of the second set of receive pins, a routed version of the test packet.

5. The apparatus of claim 2 , further comprising a different set of switch circuits configured to couple, when enabled, one or more of the second set of receive pins to a corresponding one or more of the second set of transmit pins; and
wherein the different test circuit is further configured to enable, based on a different mapping determined based on a third test mode, a third subset of switch circuits of the different set of switch circuits, coupling a fourth subset of the second set of receive pins to a fourth subset of the second set of transmit pins.

6. The apparatus of claim 5 , wherein the third subset of switch circuits is further configured to route a different test packet, received via the fourth subset of receive pins, to the fourth subset of transmit pins, the routing bypassing the different test circuit.

7. The apparatus of claim 1 , wherein the particular set of switch circuits includes:
a particular plurality of switch circuits coupled to a given one of the first set of receive pins; and
a different plurality of switch circuits coupled to a given one of the first set of transmit pins; and
wherein the particular and different pluralities of switch circuits include one common switch circuit that, when enabled, couples the given receive pin to the given transmit pin.

8. The apparatus of claim 1 , wherein a path coupling a given receive pin of the first subset of receive pins to a respective transmit pin of the first subset of transmit pins excludes clocked gates, such that a propagation delay of a signal transition applied to the given receive pin to the signal transition appearing at the given transmit pin is based on an impedance of the path.

9. A system comprising:
a first integrated circuit included in a particular chip package, and having a first test circuit, a first set of transmit pins, a first set of receive pins, and a particular set of switch circuits; and
a second integrated circuit included in the particular chip package, and having a second test circuit, a second set of transmit pins that are coupled to respective ones of the first set of receive pins, and a second set of receive pins that are coupled to respective ones of the first set of transmit pins;
wherein the second integrated circuit is configured to send, to the first integrated circuit via the second set of transmit pins, an indication to enter a particular test mode;
wherein the first integrated circuit is configured to:
in response to the indication, enable a first subset of the particular set of switch circuits, wherein the first subset of switch circuits couples a first subset of the first set of receive pins to a first subset of the first set of transmit pins, and wherein the first subset of switch circuits is selected based on the particular test mode; and
receive, via the first subset of receive pins, a particular test packet from the second integrated circuit; and
route the particular test packet to the first subset of transmit pins, bypassing the first test circuit; and

wherein the second integrated circuit is further configured to receive, via a second subset of the second set of receive pins, a routed version of the particular test packet.

10. The system of claim 9 , wherein the first integrated circuit is further configured to send, to the second integrated circuit via the first set of transmit pins, a different indication to enter a different test mode.

11. The system of claim 10 , wherein the second integrated circuit includes a different set of switch circuits and is further configured to:
in response to the different indication, enable a first subset of the different set of switch circuits, wherein the first subset of the different set of switch circuits couples a first subset of the second set of receive pins to a first subset of the second set of transmit pins, and wherein the first subset of the different set of switch circuits is selected based on the different test mode; and
receive, via the first subset of the second set of receive pins, a different test packet from the first integrated circuit; and
route the different test packet to the first subset of the second set of transmit pins, bypassing the second test circuit; and
wherein the first integrated circuit is further configured to receive, via a second subset of the first set of receive pins, a routed version of the different test packet.

12. The system of claim 9 , wherein the second integrated circuit is further configured to send, to the first integrated circuit via the second set of transmit pins, a different indication to enter a different test mode;
wherein the first integrated circuit is further configured to:
in response to the different indication, enable a second subset of the particular set of switch circuits, wherein the second subset of switch circuits couples a second subset of the first set of receive pins to a second subset of the first set of transmit pins, and wherein the second subset of switch circuits is selected based on the different test mode, and wherein a mapping of the second subset of the first set of receive pins to the second subset of the first set of transmit pins is different than a mapping used in the particular test mode.

13. The system of claim 9 , wherein the second integrated circuit is further configured to make a comparison between the routed version of the particular test packet and an expected version of the p

Assignees

• Apple Inc

Inventors

• Faure Fabien S
• Forestier Arnaud J
• Mehta Vikram

Classifications

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/31713

  Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572) · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/2889

  Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence) · CPC title

• G01R31/31712

  Input or output aspects · CPC title