Display substrate having connection electrode pattern surround first electrode pattern and including at least two of plural of connecting electrodes which are block shapes separated from each other, manufacturing method thereof and display device having the same

US11937474B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11937474-B2
Application numberUS-202217846487-A
CountryUS
Kind codeB2
Filing dateJun 22, 2022
Priority dateAug 27, 2019
Publication dateMar 19, 2024
Grant dateMar 19, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display substrate and a manufacturing method and a display device are provided. The display substrate includes: a first electrode pattern, a connecting electrode pattern, a second electrode, and a light-emitting functional layer. The first electrode pattern is located in a display region and includes a plurality of first electrodes spaced apart from each other. The connecting electrode pattern is located in a peripheral region and includes a plurality of connecting electrodes. The second electrode is connected with the connecting electrode pattern, the second electrode and the first electrode pattern being spaced apart from each other. The light-emitting functional layer is located between the first electrode pattern and the second electrode, the connecting electrode pattern surrounds the first electrode pattern, and at least two of the plurality of connecting electrodes are each of a block shape and are spaced apart from each other.

First claim

Opening claim text (preview).

What is claimed is: 1. A display substrate, comprising: a first electrode pattern, located in a display region of the display substrate and comprising a plurality of first electrodes spaced apart from each other, each of the plurality of first electrodes being configured to receive a pixel driving signal; a connecting electrode pattern, located in a peripheral region of the display substrate and comprising a plurality of connecting electrodes; a second electrode, located in the display region and the peripheral region and connected with the connecting electrode pattern, the second electrode and the first electrode pattern being spaced apart from each other, and the second electrode being configured to receive a first power signal; and a light-emitting functional layer, located between the first electrode pattern and the second electrode, wherein the connecting electrode pattern surrounds the first electrode pattern, and at least two of the plurality of connecting electrodes are each of a block shape and are spaced apart from each other, wherein the display substrate further comprises a base substrate and a first insulation layer located on the base substrate, wherein the first electrode pattern and the connecting electrode pattern are located at a side of the first insulation layer away from the base substrate, and are in contact with the first insulation layer, respectively, wherein a portion of the first insulation layer that is located between adjacent first electrodes has a first groove. 2. The display substrate according to claim 1 , wherein a portion of the first insulation layer that is located between adjacent connecting electrodes has a second groove. 3. The display substrate according to claim 2 , wherein sizes of the first groove and the second groove in a direction perpendicular to the base substrate are equal. 4. The display substrate according to claim 2 , wherein a shape of each of the plurality of the connecting electrodes is the same as that of the first electrode. 5. The display substrate according to claim 2 , further comprising a first dummy electrode pattern, wherein the first dummy electrode pattern comprises a plurality of first dummy electrodes; and the first dummy electrode pattern is located between the connecting electrode pattern and the first electrode pattern, and a shape of each of the plurality of first dummy electrodes is the same as that of the first electrode. 6. The display substrate according to claim 5 , wherein a pattern density of the connecting electrode pattern is the same as that of the first electrode pattern, and a pattern density of the first dummy electrode pattern is the same as that of the first electrode pattern. 7. The display substrate according to claim 5 , wherein a via hole is not provided in a portion of the first insulation layer which overlaps with the plurality of first dummy electrodes in a direction perpendicular to the base substrate. 8. The display substrate according to claim 5 , further comprising a second dummy electrode pattern, wherein the second dummy electrode pattern comprises a plurality of second dummy electrodes; and the second dummy electrode pattern is located at a side of the connecting electrode pattern away from the first electrode pattern, and a shape of each of the plurality of second dummy electrodes is the same as that of the first electrode. 9. The display substrate according to claim 8 , wherein a pattern density of the second dummy electrode pattern is the same as that of the first electrode pattern. 10. The display substrate according to claim 8 , wherein a via hole is not provided in a portion of the first insulation layer which overlaps with the plurality of second dummy electrodes in a direction perpendicular to the base substrate. 11. The display substrate according to claim 5 , further comprising an insulation filling layer, wherein the insulation filling layer covers the plurality of first dummy electrodes, the plurality of first dummy electrodes and the insulation filling layer constitute a first filling layer, the first electrode pattern comprises an edge first-electrode close to the plurality of connecting electrodes, and the insulation filling layer is in contact with the plurality of connecting electrodes and the edge first-electrode, respectively. 12. The display substrate according to claim 11 , wherein the second electrode is in contact with the insulation filling layer, and the edge first-electrode and the plurality of first dummy electrodes are insulated from each other. 13. The display substrate according to claim 11 , further comprising a pixel defining layer, wherein the pixel defining layer comprises a plurality of pixel defining portions, and each of the plurality of pixel defining portions is located between adjacent first electrodes. 14. The display substrate according to claim 11 , further comprising a second filling layer, wherein the second filling layer comprises at least one second filling portion, and the second filling portion is located between adjacent connecting electrodes. 15. The display substrate according to claim 14 , wherein the second filling portion is in contact with the adjacent connecting electrodes, respectively, wherein the second filling layer comprises an insulation layer, wherein the second filling layer and the insulation filling layer are located in the same layer. 16. The display substrate according to claim 14 , wherein the insulation filling layer comprises a plurality of insulation filling portions, and each of the plurality of insulation filling portions is located between adjacent first dummy electrodes. 17. The display substrate according to claim 11 , wherein the light-emitting functional layer is in contact with the first filling layer, or the light-emitting functional layer is in contact with a part of the first filling layer. 18. A display device, comprising the display substrate according to claim 1 . 19. A manufacturing method of a display substrate, comprising: forming a first electrode pattern, the first electrode pattern being located in a display region of the display substrate and comprising a plurality of first electrodes spaced apart from each other, each of the plurality of first electrodes being configured to receive a pixel driving signal; forming a connecting electrode pattern, the connecting electrode pattern being located in a peripheral region of the display substrate and comprising a plurality of connecting electrodes; forming a second electrode, the second electrode being located in the display region and the peripheral region and connected with the connecting electrode pattern, the second electrode and the first electrode pattern being spaced apart from each other, and the second electrode being configured to receive a first power signal; and forming a light-emitting functional layer, the light-emitting functional layer being located between the first electrode pattern and the second electrode, wherein the connecting electrode pattern surrounds the first electrode pattern, and at least two of the plurality of connecting electrodes are each of a block shape and are spaced apart from each other, the manufacturing method further comprises providing a base substrate and forming a first insulation layer on the base substrate, wherein the first electrode pattern and the connecting electrode pattern are located at a side of the first insulation layer away from the base substrate, and are in contact with the first insulation layer, respectively, wherein a portion of the first insu

Assignees

Inventors

Classifications

  • Insulating layers formed between TFT elements and OLED elements · CPC title

  • Dummy elements, i.e. elements having non-functional features · CPC title

  • H10K59/131Primary

    Interconnections, e.g. wiring lines or terminals · CPC title

  • G09G3/3208Primary

    organic, e.g. using organic light-emitting diodes [OLED] · CPC title

  • combined with auxiliary electrodes · CPC title

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What does patent US11937474B2 cover?
A display substrate and a manufacturing method and a display device are provided. The display substrate includes: a first electrode pattern, a connecting electrode pattern, a second electrode, and a light-emitting functional layer. The first electrode pattern is located in a display region and includes a plurality of first electrodes spaced apart from each other. The connecting electrode patter…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/131. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 19 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).