Field effect transistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11935790-B2
Application number	US-202117370480-A
Country	US
Kind code	B2
Filing date	Jul 8, 2021
Priority date	Sep 4, 2020
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.

First claim

What is claimed is:

1. A field effect transistor comprising:
a substrate;
a source electrode on the substrate;
a drain electrode separated from the source electrode;
channels between the source electrode and the drain electrode, the channels being connected to the source electrode and the drain electrode,
the channels having a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate, the channels each include a sheet portion extending parallel to an upper surface of the substrate and a contact portion extending in a direction perpendicular to the upper surface of the substrate;
gate insulating layers in the channels; and
a gate electrode insulated from the source electrode and the drain electrode by the gate insulating layers, wherein
each corresponding gate insulating layer on a corresponding channel, among the gate insulating layers on the channels, covers the sheet portion and the contact portion of the corresponding channel without being spaced apart from the sheet portion and the contact portion of the corresponding channel.

2. The field effect transistor of claim 1 , wherein at least one of the channels includes a two-dimensional semiconductor material.

3. The field effect transistor of claim 2 , wherein the two-dimensional semiconductor material includes graphene, black phosphorus, phosphor, or a transition metal dichalcogenide.

4. The field effect transistor of claim 3 , wherein
the transition metal dichalcogenide includes a metal element and a chalcogen element,
the metal element includes one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb, and
the chalcogen element includes one of S, Se, and Te.

5. The field effect transistor of claim 2 , wherein the two-dimensional semiconductor material is doped with a conductive dopant.

6. The field effect transistor of claim 1 , wherein the channels directly contact the source electrode and the drain electrode.

7. The field effect transistor of claim 1 , further comprising:
an insulating layer between the channels adjacent to each other.

8. The field effect transistor of claim 7 , wherein the insulating layer crosses an area between the source electrode and the drain electrode.

9. The field effect transistor of claim 7 , wherein the insulating layer includes at least one of low-doped silicon, SiO 2 , Al 2 O 3 , HfO 2 , or Si 3 N 4 .

10. The field effect transistor of claim 1 , wherein the channels are separated from each other in the direction perpendicular to the substrate.

11. The field effect transistor of claim 1 , wherein a region between the channels adjacent to each other is an empty space.

12. The field effect transistor of claim 1 , wherein a thickness of a sheet portion of at least one of the channels is about 10 nm or less.

13. The field effect transistor of claim 1 , wherein the gate electrode surrounds all sides of the channels when viewed in a second cross-section formed by a plane between the source electrode and the drain electrode in the direction perpendicular to the substrate.

14. The field effect transistor of claim 1 , wherein the channels have the hollow closed cross-sectional structure when viewed in a second cross-section formed by a plane between the source electrode and the drain electrode in the direction perpendicular to the substrate.

15. The field effect transistor of claim 1 , wherein the gate electrode is inside the channels when viewed in the first cross-section.

16. A method of manufacturing a field effect transistor, the method comprising:
alternately stacking sacrificial layers and insulating layers on a substrate to provide a stack structure;
patterning the stack structure using a mask to provide a patterned stack structure;
forming a source electrode and a drain electrode on both sides of the patterned stack structure;
removing the sacrificial layers, the removing the sacrificial layers leaving the insulating layers suspended between the source electrode and the drain electrode and separated from each other in a direction perpendicular to the substrate;
forming channels by depositing a channel material on the insulating layers;
depositing a gate insulating layer on the channels;
and depositing a gate electrode on the gate insulating layer.

17. The method of claim 16 , wherein at least one of the channels include a two-dimensional semiconductor material.

18. The method of claim 17 , wherein the two-dimensional semiconductor material includes graphene, black phosphorus, phosphor, or a transition metal dichalcogenide.

19. The method of claim 18 , wherein
the transition metal dichalcogenide includes a metal element and a chalcogen element,
the metal element includes one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb, and
the chalcogen element includes one of S, Se, and Te.

20. The method of claim 16 , wherein at least one of the channels directly contacts the source electrode and the drain electrode.

21. The method of claim 16 , wherein the insulating layer crosses an area between the source electrode and the drain electrode.

22. The method of claim 16 , wherein the insulating layer includes at least one of low-doped silicon, SiO 2 , Al 2 O 3 , HfO 2 , or Si 3 N 4 .

23. The method of claim 16 , wherein
the channels are between the source electrode and the drain electrode,
the channels are connected to the source electrode and the drain electrode,
the channels have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in the direction perpendicular to the substrate.

24. The method of claim 23 , wherein the channels are separated from each other in the direction perpendicular to the substrate.

25. The method of claim 16 , wherein the gate electrode surrounds all sides of the channels when viewed in a second cross-section formed by a plane between the source electrode and the drain electrode in the direction perpendicular to the substrate.

26. The method of claim 16 , wherein the channels have the hollow closed cross-sectional structure when viewed in a second cross-section formed by a plane between the source electrode and the drain electrode in the direction perpendicular to the substrate.

27. A method of manufacturing a field effect transistor, the method comprising:
alternately stacking sacrificial layers and gate electrodes on a substrate to provide a stack structure;
patterning the stack structure using a mask to provide a patterned stack structure;
forming gate support electrodes on both sides of the patterned stack structure, the gate support electrodes being connected to the gate electrodes;
removing the sacrificial layers, the removing the sacrificial layers leaving the gate electrodes suspended between the gate support electrodes and separated from each other in a direction perpendicular to the substrate;
depositing a gate insulating layer on the gate electrode;
forming channels by depositing a channel material on the gate insulating layers; and
depositing a source electrode and a drain electrode, the source electrode and the drain electrode being connected to the channels.

28. The method of claim 27 , wherein at least one of the channels includes a two-di

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seol Minsu
• Lee Minhyun
• Kwon Junyoung
• Shin Hyeonjin
• Yoo Minseok

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10P14/3436

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

• H10P14/3406

  Carbon, e.g. diamond-like carbon · CPC title

• H10P14/3402

  characterised by the chemical composition · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title