Comparison system

Patent metadata

Field	Value
Publication number	US-11935616-B2
Application number	US-202217669565-A
Country	US
Kind code	B2
Filing date	Feb 11, 2022
Priority date	Jan 14, 2021
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

Embodiments of the disclosure provide a comparison system including at least one comparison circuit, the comparison circuit including: a common circuit, connected to a power supply signal and a ground signal, and configured to control output of the power supply signal or the ground signal based on a first signal and a second signal which are inverted; a first logical circuit, connected to the common circuit, and configured to receive a third signal and a fourth signal which are inverted, and output a first operation signal which is an exclusive OR (XOR) of the first signal and the third signal; and a second logical circuit, connected to the common circuit, and configured to receive the third signal and the fourth signal, and output a second operation signal which is a not exclusive OR (XNOR) of the first signal and the third signal.

First claim

The invention claimed is:

1. A comparison system comprising at least one comparison circuit, each of the at least one comparison circuit comprising:
a common module, connected to a power supply signal and a ground signal, and configured to control output of the power supply signal or the ground signal based on a first signal and a second signal which are inverted;
a first logical unit, connected to the common module, and configured to receive a third signal and a fourth signal which are inverted, and output a first operation signal which is an exclusive OR (XOR) of the first signal and the third signal; and
a second logical unit, connected to the common module, and configured to receive the third signal and the fourth signal, and output a second operation signal which is a not exclusive OR (XNOR) of the first signal and the third signal,
wherein the comparison system is applied to a memory system which is configured to write or read, during a read operation or a write operation, a plurality of data, and the plurality of data are divided into M bytes, each having N data,
wherein the comparison system is configured to receive the plurality of data, each used as the first signal or the third signal, and perform a first encoding operation based on a subset of the N data in each of the M bytes to generate X first check codes, each based on a subset of the N data at fixed bits among all the M bytes, and perform a second encoding operation based on all data in a subset of the M bytes to generate Y second check codes, wherein the X first check codes are configured for at least one of error detection or error correction on the N data in each of the M bytes, and the Y second check codes are configured for at least one of error detection or error correction on the M bytes; and each of M, N, X and Y is a positive natural number,
wherein the comparison system further comprises:
a second comparison module formed by a plurality of comparison circuits and configured to, during the read operation of the memory system, receive the plurality of data, the X first check codes and the Y second check codes, wherein one of the X first check codes, the Y second check codes or the plurality of data is used as the first signal or the third signal, and

wherein the second comparison module configured to perform a third encoding operation on a second subset of the N data in each of the M bytes and the X first check codes to generate X first operation codes, each corresponding to a respective one of the X first check codes, and perform a fourth encoding operation on all data in a second subset of the M bytes and the Y second check codes to generate Y second operation codes, each corresponding to a respective one of the Y second check codes, wherein the third encoding operation is an XNOR or XOR operation, and the fourth encoding operation is an XNOR or XOR operation.

2. The comparison system of claim 1 , wherein the common module comprises:
a first common unit, connected to the power supply signal and configured to control output of the power supply signal based on the first signal and the second signal; and
a second common unit, connected to the ground signal and configured to control output of the ground signal based on the first signal and the second signal,
wherein the first logical unit is connected between the first common unit and the second common unit, and the second logical unit is connected between the first common unit and the second common unit.

3. The comparison system of claim 2 , wherein the first common unit comprises:
a zeroth P-channel Metal Oxide Semiconductor (PMOS) transistor, having a gate for receiving the first signal and a source connected to the power supply signal; and
a seventh PMOS transistor, having a gate for receiving the second signal and a source connected to the power supply signal; and
the second common unit comprises:
a zeroth N-channel Metal Oxide Semiconductor (NMOS) transistor, having a gate for receiving the first signal and a source connected to the ground signal; and
a seventh NMOS transistor, having a gate for receiving the second signal and a source connected to the ground signal.

4. The comparison system of claim 3 , wherein the first logical unit comprises:
a first PMOS transistor, having a gate for receiving the fourth signal and a source connected to a drain of the zeroth PMOS transistor;
a first NMOS transistor, having a gate for receiving the third signal, a drain connected to a drain of the first PMOS transistor, and a source connected to a drain of the zeroth NMOS transistor;
a fourth PMOS transistor, having a gate for receiving the third signal and a source connected to a drain of the seventh PMOS transistor; and
a fourth NMOS transistor, having a gate for receiving the fourth signal, a drain connected to a drain of the fourth PMOS transistor, and a source connected to a drain of the seventh NMOS transistor.

5. The comparison system of claim 3 , wherein the second logical unit comprises:
a second PMOS transistor, having a gate for receiving the third signal and a source connected to a drain of the zeroth PMOS transistor;
a second NMOS transistor, having a gate for receiving the fourth signal, a drain connected to a drain of the second PMOS transistor, and a source connected to a drain of the zeroth NMOS transistor;
a fifth PMOS transistor, having a gate for receiving the fourth signal and a source connected to a drain of the seventh PMOS transistor; and
a fifth NMOS transistor, having a gate for receiving the third signal, a drain connected to a drain of the fifth PMOS transistor, and a source connected to a drain of the seventh NMOS transistor.

6. The comparison system of claim 1 , comprising a first comparison module formed by the plurality of comparison circuits and configured to, during the write operation of the memory system, receive the plurality of data and perform comparison to generate the X first check codes and the Y second check codes.

7. The comparison system of claim 6 , wherein the first comparison module comprises:
a plurality of first comparison units, each of which configured to, during the write operation of the memory system, receive a third subset of the N data in each of the M bytes and perform comparison and output a respective one of the X first check codes, wherein the third subset of the N data received by each of the plurality of first comparison units are from a respective different combination of bits in the M bytes; and
a plurality of second comparison units, each of which configured to, during the write operation of the memory system, receive all data in a respective subset of the M bytes and perform comparison and output a respective one of the Y second check codes, wherein the data received by each of the plurality of second comparison units are from a respective different subset of the M bytes.

8. The comparison system of claim 7 , wherein M is 16, N is 8, X is 3 and Y is 5; a number of the plurality of first comparison units is 3, and a number of the plurality of second comparison units is 5.

9. The comparison system of claim 1 , wherein the second comparison module comprises:
a plurality of third comparison units, each configured to, during the read operation of the memory system, receive and compare a third subset of the N data in each of the M bytes, and output a first updated check code, wherein the third subset of the N data received by each of the third comparison units are from a respective different combination of bits in the M bytes;
a plurality of fourth comparison units, each configured to, during the read operation of the memory system, receive and compare all data in a fourth subset of the M bytes, and output a second updated check code

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Kangling

Classifications

• G11C7/1039 Primary

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• H03K19/017509 Primary

  Interface arrangements · CPC title

• H03K19/17784

  for supply voltage · CPC title