Overlaying on locally dispositioned patterns by ML based dynamic digital corrections (ML-DDC)

Patent metadata

Field	Value
Publication number	US-11934762-B2
Application number	US-202117396453-A
Country	US
Kind code	B2
Filing date	Aug 6, 2021
Priority date	Aug 6, 2021
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

First claim

What is claimed is:

1. A system comprising:
a memory containing computer-readable instructions; and
a processor configured to read the computer-readable instructions, that cause the processor to:
receive a substrate layout design comprising a design connection point;
receive chip-group layout design comprising metadata defining a chip-group comprising a chip-group connection point;
generate a digital exposure group based on the substrate layout design and the chip-group layout design;
pattern a substrate with the design connection point and placing the chip-group connection point based on the digital exposure group;
measure a displacement of the chip-group connection point relative to the design connection point; and
determine, using a trained machine learning (ML) model, a transformed pixel model comprising a connection path from the design connection point to the chip-group connection point.

2. The system of claim 1 , wherein the computer-readable instructions further cause the processor to optically expose the transformed pixel model to the substrate, electrically coupling the chip-group connection point to the design connection point.

3. The system of claim 2 , wherein the computer-readable instructions further cause the processor to:
operate an ML model; and
train the ML model with a plurality of training pixel models, each training pixel model defining a path between a training design connection point and a training chip-group connection point of a training substrate design layer.

4. The system of claim 3 wherein the plurality of training pixel models is based on one or more of historical pixel model data or simulated pixel model data.

5. The system of claim 4 wherein the ML model comprises one of a supervised or unsupervised ML model, configured as a classification ML model.

6. The system of claim 1 , wherein the computer-readable instructions further cause the processor to determine whether the measured displacement of the chip-group connection point relative to the design connection point is different than a placement of the chip-group connection, based on the substrate layout design.

7. The system of claim 6 , wherein measuring a displacement of the chip-group comprises measuring placement of the chip-group with one of a metrology tool or a simulation.

8. A computer program product comprising:
a non-transitory computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code being executable by one or more processors to:
receive a substrate layout design comprising a design connection point;
receive chip-group layout design comprising metadata defining a chip-group comprising a chip-group connection point;
generate a digital exposure group based on the substrate layout design and the chip-group layout design;
pattern a substrate with the design connection point and placing the chip-group based on the digital exposure group;
measure a displacement of the chip-group connection point relative to the design connection point; and
determine, using a trained machine learning (ML) model, a transformed pixel model comprising a connection path from the design connection point to the chip-group connection point.

9. The computer program product of claim 8 , wherein the program code further causes the processor to optically expose the transformed pixel model to the substrate, electrically coupling the chip-group connection point to the design connection point.

10. The computer program product of claim 9 , wherein the program code further causes the processor to:
operate an ML model; and
train the ML model with a plurality of training pixel models, each training pixel model defining a path between a training design connection point and a training chip-group connection point of a training substrate design layer.

11. The computer program product of claim 10 wherein the plurality of pixel models is based on one or more of historical pixel model data or simulated pixel model data.

12. The computer program product of claim 11 wherein the ML model comprises one of a supervised or unsupervised ML model, configured as a classification ML model.

13. The computer program product of claim 8 , wherein the program code causes the processor to determine that the measured displacement of the chip-group connection point relative to the design connection point is different than a placement of the chip-group connection, based on the substrate layout design.

14. The computer program product of claim 13 , wherein measuring a displacement of the chip-group comprises measuring placement of the chip-group with one of a metrology tool or a simulation.

15. A method comprising:
receiving a substrate layout design comprising a design connection point;
receiving chip-group layout design comprising metadata defining a chip-group comprising a chip-group connection point;
generating a digital exposure group based on the substrate layout design and the chip-group layout design;
patterning a substrate with the design connection point and placing the chip-group based on the digital exposure group;
measuring a displacement of the chip-group connection point relative to the design connection point; and
determining, using a trained machine learning (ML) model, a transformed pixel model comprising a connection path from the design connection point to the chip-group connection point.

16. The method of claim 15 further comprising optically exposing the transformed pixel model to the substrate, electrically coupling the chip-group connection point to the design connection point.

17. The method of claim 16 further comprising:
operating an ML model; and
training the ML model with a plurality of training pixel models, each training pixel model defining a path between a training design connection point and a training chip-group connection point of a substrate design layer.

18. The method of claim 17 wherein the plurality of pixel models is based on one or more of historical pixel model data or simulated pixel model data.

19. The method of claim 18 wherein the ML model comprises one of a supervised or unsupervised ML model, configured as a classification ML model.

20. The method of claim 15 further comprising determining that the measured displacement of the chip-group connection point relative to the design connection point is different than a placement of the chip-group connection, based on the substrate layout design.

Assignees

• Applied Materials Inc

Inventors

• Coskun Tamer
• Kemeldinov Aidyn
• Kang Chung-Shin
• Hollerbach Uwe
• Laidig Thomas L

Classifications

• H10P72/50

  for positioning, orientation or alignment · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06N20/00

  Machine learning · CPC title