Circuits and group III-nitride high-electron mobility transistors with buried p-type layers improving overload recovery and process for implementing the same

Patent metadata

Field	Value
Publication number	US-11929428-B2
Application number	US-202117321992-A
Country	US
Kind code	B2
Filing date	May 17, 2021
Priority date	May 17, 2021
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

An apparatus includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a recovery enhancement circuit configured to reduce an impact of an overload received by the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

First claim

What is claimed is:

1. An apparatus, comprising:
a substrate;
a group III-Nitride barrier layer;
a source electrically coupled to the group III-Nitride barrier layer;
a gate on the group III-Nitride barrier layer;
a drain electrically coupled to the group III-Nitride barrier layer;
a p-region being arranged at or below the group III-Nitride barrier layer;
a recovery enhancement circuit configured to reduce an impact of an overload received by the gate; and
a group III-Nitride buffer layer on the substrate,
wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain; and
wherein the group III-Nitride barrier layer is arranged on the group III-Nitride buffer layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride buffer layer.

2. An apparatus, comprising:
a substrate;
a group III-Nitride barrier layer;
a source electrically coupled to the group III-Nitride barrier layer;
a gate on the group III-Nitride barrier layer;
a drain electrically coupled to the group III-Nitride barrier layer;
a p-region being arranged at or below the group III-Nitride barrier layer;
a recovery enhancement circuit configured to reduce an impact of an overload received by the gate;
a group III-Nitride back barrier layer on the substrate; and
a group III-Nitride channel layer on the group III-Nitride back barrier layer,
wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain; and
wherein the group III-Nitride barrier layer is on the group III-Nitride channel layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III-Nitride channel layer.

3. An apparatus, comprising:
a substrate;
a group III-Nitride barrier layer;
a source electrically coupled to the group III-Nitride barrier layer;
a gate on the group III-Nitride barrier layer;
a drain electrically coupled to the group III-Nitride barrier layer;
a p-region being arranged at or below the group III-Nitride barrier layer; and
a recovery enhancement circuit configured to provide a bias voltage and/or a dynamic electrical pulse in order to reduce an impact of an overload received by the gate,
wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

4. The apparatus of claim 3 wherein the recovery enhancement circuit is further configured provide the bias voltage and/or the dynamic electrical pulse in order to a reduce recovery time, reduce a gate lag, reduce an impact of gate lag, reduce an increase of gate lag, reduce an impact of the overload, and/or reduce gate lag trapping effects.

5. The apparatus of claim 3 wherein the recovery enhancement circuit is configured provide the bias voltage and/or the dynamic electrical pulse to the p-region in response to an overload detection circuit.

6. The apparatus of claim 3 wherein the recovery enhancement circuit is configured provide the bias voltage and/or the dynamic electrical pulse to the gate in response to an overload detection circuit.

7. The apparatus of claim 3 wherein the recovery enhancement circuit is configured provide the bias voltage and/or the dynamic electrical pulse to the drain in response to an overload detection circuit.

8. The apparatus of claim 3 further comprising an overload detection circuit, wherein the recovery enhancement circuit is configured to provide the bias voltage and/or the dynamic electrical pulse responsive to the overload detection circuit.

9. The apparatus of claim 8 wherein the overload detection circuit comprises one or more of the following: circuitry configured to detect a high voltage level, circuitry configured to detect a high current level, circuitry configured to detect a high voltage level signal, and circuitry configured to detect a high current level signal.

10. The apparatus of claim 8 wherein the overload detection circuit is configured to detect an overload and thereafter operate the recovery enhancement circuit to provide the bias voltage and/or the dynamic electrical pulse.

11. The apparatus of claim 8 wherein the overload detection circuit is configured to detect the overload by detecting a high voltage level, a high current level, a high voltage level signal, and/or a high current level signal at the gate.

12. The apparatus of claim 8 wherein the overload detection circuit is further configured to detect when there is no longer a high voltage level, a high current level, a high voltage level signal, and/or a high current level signal applied to the gate and initiate operation of the recovery enhancement circuit to provide the bias voltage and/or the dynamic electrical pulse.

13. The apparatus of claim 8 wherein the overload detection circuit comprises one or more of the following: a voltage sensor, a current sensor, and a comparator.

14. The apparatus of claim 3 wherein the recovery enhancement circuit comprises one or more the following: a signal source, a signal generator, a bias voltage source, a bias voltage generator, a dynamic electrical pulse source, and a dynamic electrical pulse generator.

15. The apparatus of claim 3 further comprising a contact to the p-region and the contact electrically connecting the recovery enhancement circuit to the p-region,
wherein the recovery enhancement circuit is configured provide the bias voltage and/or the dynamic electrical pulse to the contact to the p-region in response to an overload detection circuit.

16. The apparatus of claim 3 , wherein:
a part of a source side of the substrate is free of the p-region; and
a part of a drain side of the substrate is free of the p-region.

17. The apparatus of claim 3 , further comprising a field plate, wherein the field plate is electrically coupled to the source.

18. The apparatus of claim 17 , wherein the p-region is structured and arranged to extend a limited length parallel to the group III-Nitride barrier layer such that the p-region is not located vertically below areas past the source and the drain.

19. The apparatus of claim 3 wherein the p-region is arranged under and across a length of the gate and extends toward the source and the drain.

20. The apparatus of claim 1 , wherein:
a portion of the substrate includes the p-region located vertically below the source; and
another portion of the substrate does not include the p-region located vertically below the source.

21. The apparatus of claim 1 , wherein:
the substrate does not include the p-region located vertically below the source; and
the substrate does not include the p-region located vertically below the drain.

22. The apparatus of claim 1 , wherein the p-region is structured and arranged such that no portion of the p-region is located vertically below the drain.

23. The apparatus of claim 1 , further comprising a connection to the p-region that is electrically connected to the gate.

24. The apparatus of claim 1 , further comprising a field plate, wherein the p-region is implanted.

25. The apparatus of claim 1 wherein:
a distance LGPS defines a length of a portion of the p-region from a lower corner of the gate on a source side toward the source;
a distance LGPD defines a l

Assignees

• Cree Inc
• Wolfspeed Inc

Inventors

• Smith Jr Thomas J
• Sriram Saptharishi
• Richards Iv Charles W

Classifications

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title