Integrated circuit device

Patent metadata

Field	Value
Publication number	US-11929389-B2
Application number	US-202117324492-A
Country	US
Kind code	B2
Filing date	May 19, 2021
Priority date	Sep 19, 2018
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit device comprising:
forming a lower electrode on a substrate;
forming a first dielectric layer on the lower electrode, the first dielectric layer including at least two grains and a grain boundary region that is disposed between the at least two grains, the first dielectric layer including a lower portion, an upper portion, and a middle portion that is disposed between the lower portion and the upper portion;
forming a second dielectric layer in the first dielectric layer;
forming an upper electrode on the first dielectric layer;
forming a first interface layer that is disposed between the lower electrode and the first dielectric layer; and
forming a second interface layer that is disposed between the first dielectric layer and the upper electrode,
wherein the second dielectric layer is formed in the grain boundary region of the middle portion of the first dielectric layer such that a width of the second dielectric layer in the middle portion is greater than a width of the second dielectric layer in at least one of the upper or lower portions when viewed in cross section,
the lower electrode includes titanium nitride,
the first interface layer includes titanium oxide and niobium oxide,
the first dielectric layer includes hafnium oxide and zirconium oxide,
the second dielectric layer includes aluminium oxide,
the second interface layer includes titanium oxide, and
the upper electrode includes titanium nitride.

2. The method of claim 1 , wherein the first interface layer further includes at least one of tantalum oxide, molybdenum oxide, iridium oxide, titanium oxynitride, tantalum oxynitride, niobium oxynitride, or molybdenum oxynitride.

3. The method of claim 1 , wherein the second interface layer further includes at least one of tantalum oxide, niobium oxide, molybdenum oxide, iridium oxide, titanium oxynitride, tantalum oxynitride, niobium oxynitride, or molybdenum oxynitride.

4. The method of claim 1 , wherein each of the lower electrode and the upper electrode further includes at least one of ruthenium, tantalum, niobium, iridium, molybdenum, tungsten, tantalum nitride, niobium nitride, molybdenum nitride, tungsten nitride, iridium oxide, ruthenium oxide, or strontium ruthenium oxide.

5. The method of claim 1 , wherein the first dielectric layer further includes at least one titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium strontium titanium oxide, scandium oxide, or lanthanons oxide.

6. The method of claim 1 , wherein the second dielectric layer further includes at least one of boron oxide, gallium oxide, or indium oxide.

7. The method of claim 1 , wherein the grain boundary region extends in a direction perpendicular to a top surface of the lower electrode.

8. The method of claim 1 , wherein a thickness of the first dielectric layer, in a direction perpendicular to a top surface of the lower electrode, is greater than a thickness of the second dielectric layer in the direction perpendicular to the top surface of the lower electrode.

9. A method of manufacturing an integrated circuit device comprising:
forming a lower electrode on a substrate;
forming a lower portion of a first dielectric layer on the lower electrode, the lower portion of the first dielectric layer including a plurality of grains;
forming an upper portion of the first dielectric layer on the lower portion of the first dielectric layer, the upper portion of the first dielectric layer including a plurality of grains;
forming a second dielectric layer between the lower portion and the upper portion of the first dielectric layer;
forming an upper electrode on the upper portion of the first dielectric layer;
forming a first interface layer that is disposed between the lower electrode and the lower portion of the first dielectric layer; and
forming a second interface layer that is disposed between the upper portion of the first dielectric layer and the upper electrode,
wherein the second dielectric layer is formed in a grain boundary region between the lower portion and the upper portion of the first dielectric layer such that a width of the second dielectric layer in the middle portion is greater than a width of the second dielectric layer in at least one of the upper or lower portions when viewed in cross section,
the lower electrode includes titanium nitride,
the first interface layer includes titanium oxide and niobium oxide,
each of the lower portion and the upper portion of the first dielectric layer includes hafnium oxide and zirconium oxide,
the second dielectric layer includes aluminium oxide,
the second interface layer includes titanium oxide, and
the upper electrode includes titanium nitride.

10. The method of claim 9 , wherein the grain boundary region extends in a direction perpendicular to a top surface of the lower electrode.

11. The method of claim 9 , wherein a thickness of the second dielectric layer is less than a total thickness of the lower portion and the upper portion of the first dielectric layer in a direction perpendicular to a top surface of the lower electrode.

12. A method of manufacturing an integrated circuit device comprising:
forming a lower electrode on a substrate;
forming a first dielectric layer on the lower electrode, the first dielectric layer including at least two grains and a grain boundary region that is disposed between the at least two grains, the first dielectric layer including a lower portion, an upper portion, and a middle portion that is disposed between the lower portion and the upper portion;
forming a second dielectric layer in the first dielectric layer;
forming a third dielectric layer on the upper portion of the first dielectric layer;
forming an upper electrode on the third dielectric layer;
forming a first interface layer that is disposed between the lower electrode and the first dielectric layer; and
forming a second interface layer that is disposed between the third dielectric layer and the upper electrode,
wherein the second dielectric layer is formed in the grain boundary region of the lower portion of the first dielectric layer and a width of the second dielectric in the lower portion of the first dielectric layer is greater than a width of the second dielectric in the middle portion when viewed in cross section,
the lower electrode includes titanium nitride,
the first interface layer includes titanium oxide and niobium oxide,
the first dielectric layer includes hafnium oxide and zirconium oxide,
the second dielectric layer includes aluminium oxide,
the third dielectric layer includes at least one of boron oxide, aluminium oxide, gallium oxide, indium oxide, or beryllium oxide,
the second interface layer includes titanium oxide, and
the upper electrode includes titanium nitride.

13. The method of claim 12 , wherein the grain boundary region extends in a direction perpendicular to a top surface of the lower electrode.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Youn-Soo
• Ryu Seung-Min
• Woo Chang-Su
• Jung Hyung-Suk
• Cho Kyu-Ho
• Cho Youn-Joung

Classifications

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/68 Primary

  Capacitors having no potential barriers · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10W20/038

  covering conductive structures (H10W20/037 takes precedence) · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title