Method to form high capacitance thin film capacitors (TFCs) as embedded passives in organic substrate packages

Patent metadata

Field	Value
Publication number	US-11929212-B2
Application number	US-201916392028-A
Country	US
Kind code	B2
Filing date	Apr 23, 2019
Priority date	Apr 23, 2019
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.

First claim

What is claimed is:

1. An electronic package, comprising:
a package substrate;
an organic layer over the package substrate; and
a capacitor embedded in the organic layer, wherein the capacitor comprises:
a first electrode, wherein the first electrode comprises a seam between a first conductive layer and a second conductive layer, wherein the seam is a boundary between a hydrophilic surface of the first conductive layer and a hydrophilic surface of the second conductive layer, the seam having variations in thickness across a length of the seam from surface irregularities in the hydrophilic surface of the first conductive layer and the hydrophilic surface of the second conductive layer;
a dielectric layer over the first electrode; and
a second electrode over the dielectric layer.

2. The electronic package of claim 1 , wherein the seam is characteristic of diffusion bonding between the first conductive layer and the second conductive layer.

3. The electronic package of claim 1 , wherein the dielectric layer is a ceramic material.

4. The electronic package of claim 3 , wherein the ceramic material comprises a crystalline microstructure.

5. The electronic package of claim 3 , wherein the ceramic material comprises a ceramic oxide.

6. The electronic package of claim 5 , herein the ceramic oxide comprises titanium, oxygen, and one or both of barium and strontium.

7. The electronic package of claim 3 , wherein the ceramic material comprises a ferroelectric ceramic.

8. The electronic package of claim 1 , wherein the dielectric layer has a capacitance density of 10 nF/mm 2 .

9. The electronic package of claim 1 , wherein a thickness of the dielectric layer is between 200 nm and 800 nm.

10. The electronic package of claim 1 , further comprising:
a barrier layer between the dielectric layer and the first electrode.

11. The electronic package of claim 10 , wherein the barrier layer comprises nickel.

12. The electronic package of claim 10 , wherein the barrier layer has a thickness between 500 nm and 1,000 nm.

13. The electronic package of claim 10 , wherein the second electrode directly contacts the dielectric layer.

14. An electronic system, comprising:
a board;
an electronic package over the board, wherein the electronic package comprises an embedded capacitor, wherein the embedded capacitor comprises:
a first electrode having a seam at a location between a top surface of the first electrode and a bottom surface of the first electrode, wherein the seam is a boundary between a hydrophilic surface of a first conductive layer of the first electrode and a hydrophilic surface of a second conductive layer of the first electrode, the seam having variations in thickness across a length of the seam from surface irregularities in the hydrophilic surface of the first conductive layer and the hydrophilic surface of the second conductive layer;
a dielectric layer over the first electrode; and
a second electrode over the dielectric layer; and

a die electrically coupled to the electronic package.

15. The electronic system of claim 14 , wherein the embedded capacitor is within a footprint of the die.

16. The electronic system of claim 14 , wherein the embedded capacitor is embedded in a topmost layer of the electronic package.

17. The electronic system of claim 14 , further comprising a plurality of dies electrically coupled to the electronic package.

18. The electronic system of claim 17 , wherein the plurality of dies are electrically coupled to each other by a bridge embedded in the electronic package.

19. The electronic system of claim 18 , wherein the embedded capacitor and the bridge are in the same layer of the electronic package.

Assignees

• Intel Corp

Inventors

• Paital Sameer
• Duan Gang
• Pietambaram Srinivas
• Darmawikarta Kristof

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title