Image signal processor and image processing system performing interrupt control

Patent metadata

Field	Value
Publication number	US-11924537-B2
Application number	US-202217669731-A
Country	US
Kind code	B2
Filing date	Feb 11, 2022
Priority date	Jun 17, 2021
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

An image signal processor includes a command queue circuit, an image processing engine and an interrupt control circuit. The command queue circuit stores a plurality of commands and sequentially provides the plurality of commands one by one. Each command of the plurality of commands includes an interrupt control value corresponding to each image unit of a plurality of image units. The plurality of commands are received from a control processor. The image processing engine receives the plurality of image units and sequentially processes the plurality of image units based on the plurality of commands sequentially provided from the command queue circuit. The interrupt control circuit receives the interrupt control value from the command queue circuit, determines one or more output interrupt event signals among a plurality of interrupt event signals based on the interrupt control value and generates an interrupt signal based on the output interrupt event signals.

First claim

What is claimed is:

1. An image signal processor comprising:
a command queue circuit configured to store a plurality of commands and sequentially provide the plurality of commands one by one, each command of the plurality of commands including an interrupt control value corresponding to each image unit of a plurality of image units, the plurality of commands being received from a control processor;
an image processing engine configured to receive the plurality of image units and sequentially process the plurality of image units based on the plurality of commands sequentially provided from the command queue circuit; and
an interrupt control circuit configured to receive the interrupt control value from the command queue circuit, determine one or more output interrupt event signals among a plurality of interrupt event signals based on the interrupt control value and generate an interrupt signal based on the output interrupt event signals.

2. The image signal processor of claim 1 , wherein the interrupt control circuit is configured to determine the output interrupt event signals with respect to each image unit based the interrupt control value included in each command.

3. The image signal processor of claim 1 , wherein the interrupt control circuit is configured to activate the interrupt signal when at least one of the output interrupt event signals is activated, regardless of activations of other interrupt event signals among the plurality of interrupt event signals except the output interrupt event signals.

4. The image signal processor of claim 1 , wherein the interrupt control circuit is configured to:
receive an interrupt enable value from the control processor;
determine one or more enable interrupt event signals among the output interrupt event signals based on the interrupt enable value; and
generate the interrupt signal based on the enable interrupt event signals.

5. The image signal processor of claim 4 , wherein the interrupt control circuit is configured to activate the interrupt signal when at least one of the enable interrupt event signals is activated, regardless of activations of other interrupt event signals among the plurality of interrupt event signals except the enable interrupt event signals.

6. The image signal processor of claim 1 , wherein the interrupt control circuit is configured;
determine one or more log interrupt event signals among the plurality of interrupt event signals based on the interrupt control value; and
store interrupt log information on activations of the log interrupt event signals.

7. The image signal processor of claim 6 , wherein the interrupt control circuit is configured to accumulate activations of the log interrupt event signals while each image unit is processes to store unit interrupt information corresponding to each image unit.

8. The image signal processor of claim 7 , wherein the interrupt control circuit is configured to sequentially store the unit interrupt information with respect to the plurality of image units.

9. The image signal processor of claim 7 , wherein the interrupt control circuit is configured to determine whether to store the unit interrupt information corresponding to each image unit based on activation of a portion of the log interrupt event signals.

10. The image signal processor of claim 7 , wherein each command further includes an image unit identifier indicating each image unit, and
wherein the interrupt control circuit is configured to:
receive the image unit identifier from the command queue circuit; and
store the unit interrupt information including the unit image identifier.

11. The image signal processor of claim 1 , wherein the interrupt control circuit includes:
a decision bit generator configured to generate a plurality of output decision bits indicating the output interrupt event signals based on the interrupt control value;
an output interrupt accumulation circuit configured to generate a plurality of output state bits indicating activations of the output interrupt event signals based on the plurality of interrupt event signals and the plurality of output decision bits; and
an interrupt generator configured to generate the interrupt signal based on the plurality of output state bits.

12. The image signal processor of claim 11 , wherein the output interrupt accumulation circuit includes:
an output decision register circuit configured to store the plurality of output decision bits provided from the decision bit generator;
an output comparison circuit configured to generate each of the plurality of output state bits by comparing each of the plurality of output decision bits and each of the plurality of interrupt event signals; and
an output state register circuit configured to store the plurality of output state bits.

13. The image signal processor of claim 11 , wherein the decision bit generator is configured to further generate a plurality of log decision bits indicating one or more log interrupt event signals among the plurality of interrupt event signals based on the interrupt control value, and
wherein the interrupt control circuit further includes:
a log interrupt accumulation circuit configured to generate a plurality of log state bits indicating activations of the log interrupt event signals based on the plurality of interrupt event signals and the plurality of log decision bits; and
a log storage configured to store interrupt log information including the plurality of log state bits.

14. The image signal processor of claim 13 , wherein the decision bit generator is configured to generate the plurality of output decision bits and the plurality of log decision bits with respect to each image unit based on the interrupt control value.

15. The image signal processor of claim 13 , wherein each command further includes an image unit identifier indicating each image unit, and
wherein the log storage is configured to:
receive the image unit identifier from the command queue circuit; and
store unit interrupt information including the unit image identifier with respect to each image unit.

16. The image signal processor of claim 13 , wherein the log interrupt accumulation circuit includes:
a log decision register circuit configured to store the plurality of log decision bits provided from the decision bit generator;
a log comparison circuit configured to generate each of a plurality of log state bits by comparing each of the plurality of log decision bits and each of the plurality of interrupt event signals; and
a log state register circuit configured to store the plurality of log state bits.

17. The image signal processor of claim 11 , wherein the interrupt generator includes:
an enable register circuit configured to store a plurality interrupt enable bits provided form the control processor; and
an enable comparison circuit configured to generate the interrupt signal by comparing each of the plurality output state bits and each of the plurality of interrupt enable bits.

18. An image processing system comprising:
a control processor configured to generate a plurality of commands and execute an interrupt service routine based on an interrupt signal, each command of the plurality of commands including an interrupt control value corresponding to each image unit of a plurality of image units; and
an image signal processor configured to process the plurality of image units and generate the interrupt signal, the image signal processor including:
a command queue circuit configured to store the plurality of commands and sequentially provide th

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Jinwoo
• Kang Homin
• Ahn Jaeuk
• Lee Serhoon

Classifications

• H04N23/60 Primary

  Control of cameras or camera modules · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title