Image processor

Patent metadata

Field	Value
Publication number	US-9986243-B2
Application number	US-201414228814-A
Country	US
Kind code	B2
Filing date	Mar 28, 2014
Priority date	Mar 29, 2013
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

In the multi mode, the software processing unit notifies the hardware processing unit by batch of multiple settings information sets about multiple output pictures before the hardware processing unit starts to encode an input picture, and the hardware processing unit performs continuous encoding for the output pictures, based on the settings information sets notified of by the software processing unit, without a notification signifying a completion for every picture, and upon completion of encoding for all of the output pictures, sends an interrupt notification signifying a completion of encoding to the software processing unit.

First claim

What is claimed is:

1. An image processor comprising:
a memory configured to store a target picture for image processing;
a software processing unit configure to perform image processing on a picture by software processing; and
a hardware processing unit configured to perform image processing on a picture by hardware processing,
the software processing unit having a multi mode as an operational mode of the hardware processing unit, the multi mode being a mode for encoding an input picture within a vertical synchronization period specified based on a maximum computing power of the image processor so as to generate a plurality of output pictures that are different in at least one of a picture size and a frame rate, the vertical synchronization period being a time period for encoding per picture with respect to a sequence having the highest frame rate among multiple sequences processed in multi-encoding, wherein
in the multi mode,
the software processing unit notifies the hardware processing unit by a plurality of settings information sets about a plurality of output pictures to be generated in each vertical synchronization period before the hardware processing unit starts to encode an input picture,
the hardware processing unit performs continuous encoding for the output pictures in each vertical synchronization period, based on the settings information sets notified of by the software processing unit, without a notification signifying a completion for every picture, and upon completion of encoding for all of the output pictures to be generated in each vertical synchronization period, sends an interrupt notification signifying a completion of encoding to the software processing unit, and
the hardware processing unit including:
a coding circuit configured to code an input picture;
a NAL-forming circuit configured to form NAL for the picture coded by the coding circuit; and
a control circuit configured to control the coding circuit and the NAL-forming circuit,
wherein
the settings information sets notified of by the software processing unit to the hardware processing unit is input to the NAL-forming circuit and the control circuit.

2. The image processor according to claim 1 , wherein
the software processing unit sets a picture size and a frame rate of each of a plurality of output pictures, based on a maximum picture size and a frame rate corresponding to the maximum picture size processable by the image processor, and a use of the output pictures.

3. The image processor according to claim 2 , wherein with output pictures to be generated in a plurality of continuous vertical synchronization periods being different in frame rates of the output pictures, the software processing unit notifies the hardware processing unit of information for identifying an output picture among a plurality of output pictures to be generated in each vertical synchronization period along with the settings information sets.

4. The image processor according to claim 1 , wherein the settings information sets input to the NAL-forming circuit include header information to be used to form NAL for each output picture.

5. The image processor according to claim 1 , wherein with output pictures to be generated in a plurality of continuous vertical synchronization periods being different in frame rates of the output pictures, the software processing unit notifies the hardware processing unit of information for identifying an output picture among a plurality of output pictures to be generated in each vertical synchronization period along with the settings information sets.

6. The image processor according to claim 1 ,
the software processing unit further having a high-speed mode as an operational mode of the hardware processing unit, the high-speed mode being a mode for encoding an input picture so as to generate an output picture having a picture size smaller than a maximum picture size processable by the image processor and a frame rate higher than a frame rate corresponding to the maximum picture size, wherein
in the high-speed mode,
the software processing unit notifies the hardware processing unit of settings information about output pictures before the hardware processing unit starts to encode an input picture, and the hardware processing unit performs continuous encoding for the output pictures, based on the settings information notified of by the software processing unit, without a notification signifying a completion for every picture, and upon completion of encoding for all of a specified number of the output pictures, sends an interrupt notification signifying a completion of encoding to the software processing unit.

7. The image processor according to claim 6 , wherein
the software processing unit sets a maximum frame rate of an output picture, based on a maximum picture size and a frame rate corresponding to the maximum picture size processable by the image processor, a picture size of an output picture, and a maximum clock frequency of the hardware processing unit.

8. The image processor according to claim 7 , wherein
the software processing unit notifies the hardware processing unit of information about a specified number of output pictures to be generated by continuous encoding along with the settings information.

9. The image processor according to claim 8 , wherein the settings information sets input to the NAL-forming circuit include header information to be used to form NAL for output pictures.

10. The image processor according to claim 6 , wherein
the software processing, unit notifies the hardware processing unit of information about a specified number of output pictures to be generated by continuous encoding along with the settings information.

11. The image processor according to claim 6 , wherein the settings information sets input to the NAL-forming circuit include header information to be used to form NAL for output pictures.

Assignees

• Megachips Corp

Inventors

• Saito Kazuhiro

Classifications

• H04N19/172

  the region being a picture, frame or field · CPC title

• H04N19/12

  Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264 · CPC title

• H04N19/136 Primary

  Incoming video signal characteristics or properties · CPC title

• H04N19/156

  Availability of hardware or computational resources, e.g. encoding based on power-saving criteria · CPC title

• H04N19/42

  characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) · CPC title